CUDA (Compute Unified Device Architecture) is a proprietary[3]parallel computing platform and application programming interface (API) developed by Nvidia that allows software to use certain types of graphics processing units (GPUs) for accelerated general-purpose processing, significantly broadening their utility in artificial intelligence, scientific and high-performance computing. CUDA was created in 2004 and was officially released in 2007.[4] When introduced, the name was an acronym for Compute Unified Device Architecture,[5] but Nvidia later dropped the initial meaning of the acronym and now rarely expands it.[6]
CUDA is both a software layer that manages data, giving direct access to the GPU and CPU as necessary, and a library of APIs that enable parallel computation.[7][8] In addition to drivers and runtime kernels, the CUDA platform includes compilers, libraries and developer tools to help programmers.
CUDA is written in the C programming language, but is designed to work with other programming languages including C++, Fortran, Python and Julia. This accessibility makes it easier for specialists in parallel programming to use GPU resources, in contrast to prior APIs like Direct3D and OpenGL, which require advanced skills in graphics programming.[9] CUDA-powered GPUs support programming frameworks such as OpenMP, OpenACC and OpenCL.[10][7]
The graphics processing unit (GPU) is a specialized processor. It addresses the demands of real-time high-resolution, compute-intensive tasks such as 3D graphics. By 2012, GPUs had evolved into highly parallel multi-core systems allowing efficient manipulation of large blocks of data. This design is more effective than general-purpose central processing unit (CPUs) for algorithms in situations where processing large blocks of data is done in parallel, such as:
CUDA traces to the early 2000s, when Ian Buck, a computer science PhD student at Stanford University, began experimenting with using GPUs for purposes beyond rendering graphics. Buck had become interested in GPUs during his undergraduate studies at Princeton University, initially through video gaming. After graduation, he interned at Nvidia, gaining deeper exposure to GPU architecture. At Stanford, he built an 8K gaming rig using 32 GeForce graphics cards, originally to push the limits of graphics performance in games like Quake and Doom. However, his interests shifted toward exploring the potential of GPUs for general-purpose parallel computing.[11]
To that end, Buck developed Brook, a programming language designed to enable general-purpose computing on GPUs. His work attracted support from Nvidia and the Defense Advanced Research Projects Agency (DARPA). In 2004, Nvidia hired Buck and paired him with John Nickolls,[12] then director of architecture for GPU computing. Together, they began transforming Brook into CUDA.[11] CUDA was officially released in 2007.
CUDA became central to the company's strategy of positioning GPUs as versatile hardware for scientific applications. By 2015, CUDA's development increasingly focused on accelerating machine learning and artificial neural network workloads.[13]
Ontology
The following table offers an approximate summary of the CUDA ontology.
Copy the resulting data from GPU memory to main memory
The CUDA platform is accessible to software developers through CUDA-accelerated libraries, compiler directives such as OpenACC, and extensions to industry-standard programming languages including C, C++, Fortran and Python. C/C++ programmers can use 'CUDA C/C++', compiled to PTX with nvcc (Nvidia's LLVM-based C/C++ compiler)[14] or by clang itself.[15] Fortran programmers can use 'CUDA Fortran', compiled with the PGI CUDA Fortran compiler from The Portland Group. Python programmers can use the cuPyNumeric library to accelerate applications on Nvidia GPUs.
CUDA provides both a low level API (CUDA Driver API, non single-source) and a higher level API (CUDA Runtime API, single-source). The initial CUDA SDK was made public on 15 February 2007, for Microsoft Windows and Linux. Mac OS X support was later added in version 2.0,[23] which supersedes the beta released February 14, 2008.[24] CUDA works with all Nvidia GPUs from the G8x series onwards, including GeForce, Quadro and the Tesla line. CUDA is compatible with most standard operating systems.
CUDA 8.0 comes with the following libraries (for compilation & runtime, in alphabetical order):
cuBLAS – CUDA Basic Linear Algebra Subroutines library
CUDART – CUDA Runtime library
cuFFT – CUDA Fast Fourier Transform library
cuRAND – CUDA Random Number Generation library
cuSOLVER – CUDA based collection of dense and sparse direct solvers
cuSPARSE – CUDA Sparse Matrix library
NPP – NVIDIA Performance Primitives library
nvGRAPH – NVIDIA Graph Analytics library
NVML – NVIDIA Management Library
NVRTC – NVIDIA Runtime Compilation library for CUDA C++
CUDA 8.0 comes with these other software components:
nView – NVIDIA nView Desktop Management Software
NVWMI – NVIDIA Enterprise Management Toolkit
GameWorks PhysX – is a multi-platform game physics engine
CUDA 9.0–9.2 comes with these other components:
CUTLASS 1.0 – custom linear algebra algorithms,
NVIDIA Video Decoder was deprecated in CUDA 9.2; it is now available in NVIDIA Video Codec SDK
CUDA 10 comes with these other components:
nvJPEG – Hybrid (CPU and GPU) JPEG processing
CUDA 11.0–11.8 comes with these other components:[25][26][27][28]
CUDA has several advantages over traditional general-purpose computation on GPUs (GPGPU) using graphics APIs:
Scattered reads–code can read from arbitrary addresses in memory
Unified virtual memory (CUDA4.0 and above)
Unified memory (CUDA6.0 and above)
Shared memory–CUDA exposes a fast shared memory region that can be shared among threads. This can be used as a user-managed cache, enabling higher bandwidth than is possible using texture lookups.[29]
Faster downloads and readbacks to and from the GPU
Full support for integer and bitwise operations, including integer texture lookups
Limitations
Whether for the host computer or the GPU device, all CUDA source code is now processed according to C++ syntax rules.[30] This was not always the case. Earlier versions of CUDA were based on C syntax rules.[31] As with the more general case of compiling C code with a C++ compiler, it is therefore possible that old C-style CUDA source code will either fail to compile or will not behave as originally intended.
Interoperability with rendering languages such as OpenGL is one-way, with OpenGL having access to registered CUDA memory but CUDA not having access to OpenGL memory.
Copying between host and device memory may incur a performance hit due to system bus bandwidth and latency (this can be partly alleviated with asynchronous memory transfers, handled by the GPU's DMA engine).
Threads should be running in groups of at least 32 for best performance, with total number of threads numbering in the thousands. Branches in the program code do not affect performance significantly, provided that each of 32 threads takes the same execution path; the SIMD execution model becomes a significant limitation for any inherently divergent task (e.g. traversing a space partitioning data structure during ray tracing).
No emulation or fallback functionality is available for modern revisions.
Valid C++ may sometimes be flagged and prevent compilation due to the way the compiler approaches optimization for target GPU device limitations.
C++ run-time type information (RTTI) and C++-style exception handling are only supported in host code, not in device code.
In single-precision on first generation CUDA compute capability 1.x devices, denormal numbers are unsupported and are instead flushed to zero, and the precision of both the division and square root operations are slightly lower than IEEE 754-compliant single precision math. Devices that support compute capability 2.0 and above support denormal numbers, and the division and square root operations are IEEE 754 compliant by default. However, users can obtain the prior faster gaming-grade math of compute capability 1.x devices if desired by setting compiler flags to disable accurate divisions and accurate square roots, and enable flushing denormal numbers to zero.[32]
Unlike OpenCL, CUDA-enabled GPUs are only available from Nvidia as it is proprietary.[33][3] Attempts to implement CUDA on other GPUs include:
Project Coriander: Converts CUDA C++11 source to OpenCL 1.2 C. A fork of CUDA-on-CL intended to run TensorFlow.[34][35][36]
GPUOpen HIP: A thin abstraction layer on top of CUDA and ROCm intended for AMD and Nvidia GPUs. Has a conversion tool for importing CUDA C++ source. Supports CUDA 4.0 plus C++11 and float16.
ZLUDA is a drop-in replacement for CUDA on AMD GPUs and formerly Intel GPUs with near-native performance.[38] The developer, Andrzej Janik, was separately contracted by both Intel and AMD to develop the software in 2021 and 2022, respectively. However, neither company decided to release it officially due to the lack of a business use case. AMD's contract included a clause that allowed Janik to release his code for AMD independently, allowing him to release the new version that only supports AMD GPUs.[39]
ChipStar can compile and run CUDA/HIP programs on advanced OpenCL 3.0 or Level Zero platforms.[40]
SCALE is a CUDA-compatible programming toolkit for ahead of time compilation of CUDA source code on AMD GPUs, aiming to expand support for other GPUs in the future.[41]
Example
This example code in C++ loads a texture from an image into an array on the GPU:
voidfoo(){cudaArray*cu_array=nullptr;// Allocate arraycudaChannelFormatDescdescription=cudaCreateChannelDesc<float>();cudaMallocArray(&cu_array,&description,width,height);// Copy image data to arraycudaMemcpy2DToArray(cu_array,0,0,image,width*sizeof(float),width*sizeof(float),height,cudaMemcpyHostToDevice);// Resource description (what the texture points to)cudaResourceDescresDesc={};resDesc.resType=cudaResourceTypeArray;resDesc.res{.array{.array=cu_array}};// Texture description (sampling parameters)cudaTextureDesctexDesc={};texDesc.addressMode={cudaAddressModeClamp,cudaAddressModeClamp};texDesc.filterMode=cudaFilterModePoint;texDesc.readMode=cudaReadModeElementType;texDesc.normalizedCoords=0;// use unnormalized integer coordinates// Create the texture objectcudaTextureObject_ttexObj=0;cudaCreateTextureObject(&texObj,&resDesc,&texDesc,nullptr);// Run kernel - pass the texture object as a parameterdim3blockDim(16,16,1);dim3gridDim((width+blockDim.x-1)/blockDim.x,(height+blockDim.y-1)/blockDim.y,1);kernel<<<gridDim,blockDim>>>(texObj,d_data,height,width);// Clean upcudaDestroyTextureObject(texObj);// cudaFreeArray(cu_array); // when you are done with the array}__global__voidkernel(cudaTextureObject_ttexObj,float*odata,intheight,intwidth){intx=blockIdx.x*blockDim.x+threadIdx.x;inty=blockIdx.y*blockDim.y+threadIdx.y;if(x<width&&y<height){floatc=tex2D<float>(texObj,x,y);odata[y*width+x]=c;}}
Below is an example given in Python that computes the product of two arrays on the GPU. The unofficial Python language bindings can be obtained from PyCUDA.[42]
importnumpyimportpycuda.autoinitfromnumpy.typingimportNDArray,float32frompycuda.compilerimportSourceModulefrompycuda.driverimportFunction,In,Outmod:SourceModule=SourceModule("""__global__ void multiply_them(float* dest, float* a, float* b) { const int i = threadIdx.x; dest[i] = a[i] * b[i];}""")multiply_them:Function=mod.get_function("multiply_them")a:NDArray[float32]=numpy.random.randn(400).astype(numpy.float32)b:NDArray[float32]=numpy.random.randn(400).astype(numpy.float32)dest:NDArray[float32]=numpy.zeros_like(a)multiply_them(Out(dest),In(a),In(b),block=(400,1,1))print(dest-a*b)
Additional Python bindings to simplify matrix multiplication operations can be found in the program pycublas.[43]
Note on notation: compute capability X.Y is also written as SMXY or sm_XY (e.g. 10.3 as SM103 or sm_103) in professional Nvidia software and the code Nvidia has contributed to LLVM.[45]
Below is a table of supported CUDA compute capabilities based on the CUDA SDK version and microarchitecture, listed by code name:
CUDA SDK support vs. microarchitecture (cell: compute capability)
RTX PRO 6000 Blackwell Workstation, RTX PRO 5500 Blackwell Workstation, RTX PRO 5000 Blackwell, RTX PRO 4500 Blackwell Workstation, RTX PRO 4000 Blackwell, RTX PRO 2000 Blackwell
RTX PRO 6000 Blackwell Server, RTX PRO 4500 Blackwell Server
↑CUDA Toolkit 13.0 renamed the SM101 for Thor GPUs to SM110.
Version features and specifications
Note: A GPU with a higher compute capacity is able to execute PTX code meant for a GPU of a lower range of compute capacities. However, it is possible to compile CUDA code into a form that only works on one family (same "X") of GPUs; if existing code is compiled this way, recompilation will be needed for it to work on a newer GPU.[45]
Feature support (unlisted features are supported for all compute capabilities)
oneAPI is an initiative based in open standards, created to support software development for multiple hardware architectures.[125] The oneAPI libraries must implement open specifications that are discussed publicly by the Special Interest Groups, offering the possibility for any developer or organization to implement their own versions of oneAPI libraries.[126][127]
Originally made by Intel, other hardware adopters include Fujitsu and Huawei.
Unified Acceleration Foundation (UXL)
Unified Acceleration Foundation (UXL) is a new technology consortium working on the continuation of the OneAPI initiative, with the goal to create a new open standard accelerator software ecosystem, related open standards and specification projects through Working Groups and Special Interest Groups (SIGs). The goal is to offer open alternatives to Nvidia's CUDA. The main companies behind it are Intel, Google, ARM, Qualcomm, Samsung, Imagination, and VMware.[128]
SYCL – an open standard from Khronos Group for programming a variety of platforms, including GPUs, with single-source modern C++, similar to higher-level CUDA Runtime API (single-source)
Vulkan – low-level, high-performance 3D graphics and computing API
↑"John Nickolls Obituary – Los Altos, CA". The Mercury News. 2011-09-29. Retrieved 2025-11-23. John Richard Nickolls, who passed away in Los Altos, California on August 13, 2011 after a courageous battle against cancer. He was born on March 6, 1950 to Kenneth and Kathryn Nickolls and grew up in Wilbraham, Massachusetts.
↑In the Whitepapers the Tensor Core cube diagrams represent the Dot Product Unit Width into the height (4 FP16 for Volta and Turing, 8 FP16 for A100, 4 FP16 for GA102, 16 FP16 for GH100). The other two dimensions represent the number of Dot Product Units (4x4 = 16 for Volta and Turing, 8x4 = 32 for Ampere and Hopper). The resulting gray blocks are the FP16 FMA operations per cycle. Pascal without Tensor core is only shown for speed comparison as is Volta V100 with non-FP16 datatypes.
↑No more than one scheduler can issue 2 instructions at once. The first scheduler is in charge of warps with odd IDs. The second scheduler is in charge of warps with even IDs.
12Jia, Zhe; Maggioni, Marco; Staiger, Benjamin; Scarpazza, Daniele P. (2018). "Dissecting the NVIDIA Volta GPU Architecture via Microbenchmarking". arXiv:1804.06826 [cs.DC].
↑Jia, Zhe; Maggioni, Marco; Smith, Jeffrey; Daniele Paolo Scarpazza (2019). "Dissecting the NVidia Turing T4 GPU via Microbenchmarking". arXiv:1903.07486 [cs.DC].
↑Note that Jia, Zhe; Maggioni, Marco; Smith, Jeffrey; Daniele Paolo Scarpazza (2019). "Dissecting the NVidia Turing T4 GPU via Microbenchmarking". arXiv:1903.07486 [cs.DC]. disagrees and states 2 KiB L0 instruction cache per SM partition and 16 KiB L1 instruction cache per SM
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