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GeezerVison is showing en.wikipedia.org — Category:Instruction processing - Wikipedia

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Wikimedia Commons has media related to Instruction processing.

This category contains articles related to instruction processing by microprocessors.

Subcategories

This category has the following 6 subcategories, out of 6 total.

G

  • GPGPU (2 C, 28 P)

M

  • Machine code (21 P)

S

  • SIMD computing (1 C, 45 P)
  • Speculative execution (1 C, 4 P)
  • Superscalar microprocessors (48 P)

V

  • Very long instruction word computing (38 P)

Pages in category "Instruction processing"

The following 69 pages are in this category, out of 69 total. This list may not reflect recent changes.

A

  • Address generation unit
  • Anticiparallelism
  • Application-specific instruction set processor

B

  • Barrel processor
  • Berkeley RISC
  • Branch (computer science)
  • Branch misprediction
  • Branch predictor
  • Branch queue
  • Branch target predictor
  • Burroughs B6x00-7x00 instruction set

C

  • Control store
  • Cycles per instruction

D

  • Decoupled architecture
  • Degree of parallelism
  • Delay slot

E

  • Execute instruction
  • Explicitly parallel instruction computing

G

  • General-purpose computing on graphics processing units

H

  • Hardware reset
  • Hardware scout
  • Hazard (computer architecture)

I

  • Instruction cycle
  • Instruction-level parallelism
  • Instruction window
  • Instructions per cycle
  • Interlock (engineering)

M

  • Memory barrier
  • Memory type range register
  • Memory-level parallelism
  • Micro-operation
  • Microarchitecture
  • Microcode
  • MIL-STD-1750A
  • Millicode
  • Minimal instruction set computer
  • Model-specific register
  • Multithreading (computer architecture)

N

  • No instruction set computing

O

  • Operand forwarding
  • Orthogonal instruction set
  • Out-of-order execution

P

  • Instruction pipelining
  • Pipeline (computing)
  • Classic RISC pipeline
  • Pipeline stall
  • Predication (computer architecture)
  • Instruction prefetch
  • Prefetch input queue

R

  • Random logic
  • Re-order buffer
  • Register window
  • Repeat instruction
  • Reservation station
  • Reset vector
  • Runahead

S

  • Scoreboarding
  • Instruction set architecture
  • Slipstream (computer science)
  • Speculative execution
  • Speculative multithreading

T

  • Tomasulo's algorithm
  • Transport triggered architecture
  • TRIPS architecture

U

  • Unicore

V

  • Very long instruction word
  • VIA PadLock

W

  • Wide-issue

Z

  • Zero instruction set computer
Retrieved from "https://en.wikipedia.org/w/index.php?title=Category:Instruction_processing&oldid=934961838"
Categories:
  • Computer architecture
  • Microprocessors
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