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In VHDL simulations, all assignments to signals (a VHDL concept that represents a net connecting different components together) occur with some infinitesimal delay, known as delta delay, unless a delay is specified.^[1] Technically, delta delay is of no measurable unit, but from a digital electronics hardware design perspective one should think of delta delay as being the smallest time unit one could measure, such as a femtosecond (fs).