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A ferroelectric field-effect transistor (Fe FET) is a type of field-effect transistor that includes a ferroelectric material sandwiched between the gate electrode and source–drain conduction region of the device (the channel). Permanent electrical field polarisation in the ferroelectric causes this type of device to retain the transistor's state (on or off) in the absence of any electrical bias.

FeFET based devices are used in FeFET memory – a type of single-transistor non-volatile memory and also in artificial neuron circuits ^[1].

In 1955, Ian Munro Ross filed a patent for a FeFET, or MFSFET. Its structure was like that of a modern inversion-channel MOSFET, but ferroelectric material was used as a dielectric/insulator instead of oxide.^[2] Use of a ferroelectric (triglycine sulfate) in a solid-state memory was proposed by Moll and Tarui in 1963 using a thin-film transistor.^[3] Further research occurred in the 1960s, but the retention characteristics of the thin-film-based devices was unsatisfactory.^[4] Early devices based on field-effect transistors used bismuth titanate (Bi
₄Ti
₃O
₁₂) ferroelectric, or Pb
_1−xLn
_xTiO
₃ (PLT) and related mixed zirconate/titanates (PLZT).^[4] In the late 1980s, ferroelectric RAM was developed, using a ferroelectric thin film as capacitor, connected to an addressing FET.^[4]

FeFET-based memory devices are read using voltages below the coercive voltage for the ferroelectric.^[5]

Issues involved in realising a practical FeFET memory device include (as of 2006): choice of a high-permitivity, highly insulating layer between ferroelectric and gate; issues with high remanent polarisation of ferroelectrics; limited retention time (only a few days instead of required 10 years).^[6]

Provided that the ferroelectric layer can be scaled accordingly, FeFET-based memory devices are expected to scale (shrink) as well as MOSFET devices; however a limit of ~20 nm laterally may exist^[7] (the superparaelectric limit, aka ferroelectric limit). Other challenges to feature shrinks include: reduced film thickness causing additional (undesired) polarisation effects; charge injection; and leakage currents.^[6]

Research and development

In 2017, FeFET based non-volatile memory was reported as having been built at 22 nm node using FDSOI CMOS (fully depleted silicon on insulator) with hafnium dioxide (HfO
₂) as the ferroelectric. The smallest FeFET cell size reported was 0.025 μm². The devices were built as 32 Mbit arrays, using set/reset pulses of ~10 ns duration at 4.2 V. The devices showed endurance of 10⁵ cycles and data retention up to 300 °C.^[8]

As of 2017, the startup Ferroelectric Memory Company is attempting to develop FeFET memory into a commercial device, based on hafnium dioxide. The company's technology is claimed to scale to modern process node sizes and to integrate with contemporary production processes, i.e. HKMG, and is easily integrable into conventional CMOS processes, requiring only two additional masks.^[9]

• Ferroelectric RAM, RAM that uses a ferroelectric material in the capacitor of a conventional DRAM structure