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numeric_std is a library package defined for VHDL. It provides arithmetic functions for vectors. Overrides of std_logic_vector are defined for signed and unsigned arithmetic. It defines numeric types and arithmetic functions for use with synthesis tools. Two numeric types are defined: UNSIGNED (represents UNSIGNED number in vector form) and SIGNED (represents a SIGNED number in vector form). The base element type is type STD_LOGIC. The leftmost bit is treated as the most significant bit. Signed vectors are represented in two's complement form. This package contains overloaded arithmetic operators on the SIGNED and UNSIGNED types. The package also contains useful type conversions functions.

It is typically included at the top of a design unit:

  library ieee;
  use ieee.std_logic_1164.all;	-- standard unresolved logic UX01ZWLH-
  use ieee.numeric_std.all;       -- for the signed, unsigned types and arithmetic ops

The alternative numeric package ieee.std_logic_arith should not be used for new designs. This package does not provide overrides for mixing signed and unsigned functions. This package includes definitions for the following (not all of which are synthesizable):^[1]

Operators and functions

Sign changing operators

Arithmetic operators

Note: the second argument of /, rem, or mod must be nonzero.

Comparison operators

Shift and rotate functions

SHIFT_LEFT
SHIFT_RIGHT
ROTATE_LEFT
ROTATE_RIGHT
sll
srl
rol
ror

Resize function

RESIZE(v,n)

Note: when increasing the size of a signed vector the leftmost bits are filled with the sign bit, while truncation retains the sign bit along with the (n-1) rightmost bits. For an unsigned vector, a size increase fills the leftmost bits with zero, while truncation retains n rightmost bits.

Conversion functions

TO_INTEGER
TO_UNSIGNED
TO_SIGNED

Note: The latter two functions each require a second argument specifying the length of the resulting vector.

Logical operators

not
and
or
nand
nor
xor
xnor

Match function

STD_MATCH

Note: compares argument vectors element by element, but treats any bit with the value '-' as matching any other STD_ULOGIC value. Returns false if any argument bit is 'U', 'X', 'W', or 'Z'.

Special translation function

TO_01

Note: 'H' is translated to '1' and 'L' is translated to '0'; this function takes an optional second argument XMAP, which can be any of the std_logic values, but defaults to '0'. Any value besides 01LH in the input argument results in all bits being set to XMAP, with a warning issued.

References

↑ 1076.3 IEEE Standard VHDL Synthesis Packages

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