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GeezerVison is showing github.com — NetFPGA.github.io/NetFPGA-CML.html at main · NetFPGA/NetFPGA.github.io Expand file tree/ Copy pathNetFPGA-CML.htmlMore file actions 158 lines (157 loc) · 6.91 KB / Copy pathNetFPGA-CML.htmlFile metadata and controls158 lines (157 loc) · 6.91 KB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 --- layout: page --- <h1>NetFPGA CML</h1> <br> <div id="accordion-CML1" class="accordion"> <div class="" data-toggle="collapse" href="#collapse-CML1"> <button class="card-title" ><h2>Details  </h2></button> </div> <div id="collapse-CML1" class="collapse show" data-parent="#accordion-CML1"> <p>The NetFPGA-1G-CML is an FPGA-based PCI Express board with Gigabit Ethernet I/O, an x4 gen2 PCIe adapter card incorporating Xilinx’s Kintex-7 325T FPGA. It is ideal for the development of highly complex, low bandwidth applications.</p> <p>Features list:</p> <ul> <li>Field Programmable Gate Array (FPGA) Logic <ul> <li><a href="http://www.xilinx.com/products/silicon-devices/fpga/kintex-7/" >Xilinx Kintex-7 325T</a></li> <li>326,080 logic cells</li> <li>16,020 Kbit block RAM</li> <li>up to 4,000 Kbit distributed RAM</li> <li>Fully programmable by the user</li> </ul></li> <li>Gigabit Ethernet networking ports <ul> <li>Four 10/100/1000 Ethernet PHYs with RGMII</li> <li>Wire-speed processing on all ports at all time using FPGA logic</li> </ul></li> <li>Quad Data Rate Static Random Access Memory (QDRII+ SRAM) <ul> <li>Suitable for storing and forwarding table data</li> <li>450MHz Quad data rate (1.8 Giga transactions every second), synchronous with the logic</li> <li>36 MBit (4.5 MBytes) QDRII+ memory</li> <li><a href="http://www.cypress.com/?mpn=CY7C2263KV18-450BZXI" >Cypress: CY7C2263KV18</a></li> </ul></li> <li>Double-Date Rate Random Access Memory (DDR3 DRAM) <ul> <li>Suitable for packet buffering</li> <li>x8 DDR3 on-board device</li> <li>800MHz clock (1600MT/s)</li> <li>12.8 Gbps peak memory throughput</li> <li>Capacity: 512MByte</li> <li>Micron: MT41K512M8</li> </ul></li> <li>PCI Express Gen. 2 <ul> <li>Second generation PCI Express interface, 5Gbps/lane</li> <li>4 lanes (x4)</li> <li>Hard IP</li> <li>Provides CPU access to memory-mapped registers and memory on the NetFPGA hardware</li> </ul></li> <li>Storage<ul> <li>SD-card slot</li> <li>1Gbit FLASH</li> </ul></li> <li>Expansion Interfaces <ul> <li>Fully compliant VITA-57 FMC HPC connector, including 4 high-speed serial links (GTX)</li> <li>Two Digilent PMOD expansion connectors</li> </ul></li> <li>Additional Features <ul> <li>32-bit PIC microcontroller</li> <li>USB microcontroller</li> <li>Real Time clock</li> <li>Crypto-authentication chip</li> <li>User LEDs & Push Buttons</li> </ul></li> <li>Standard PCIe Form Factor <ul> <li>Standard PCIe card</li> <li>3/4 length, full height</li> </ul></li> <li>Flexible, Open-source code</li> </ul> </div> </div> <br> <hr> <div id="accordion-CML2" class="accordion"> <div class="collapsed" data-toggle="collapse" href="#collapse-CML2"> <button class="card-title" ><h2>Downloads  </h2></button> </div> <div id="collapse-CML2" class="collapse" data-parent="#accordion-CML2"> <p>To see the NetFPGA-1G-CML repository and Wiki you will need to <a href="{% link CML-reg-form.html %}" >register</a>.</p> <h3>Reference Projects</h3> <table class="downloads"> <tr> <th>Title</th> <th>Organisation</th> <th>Documentation</th> </tr> <tr> <td>Ethernet Interface Loopback Test</td> <td>CML / University of Cambridge</td> <td><a href="https://github.com/NetFPGA/NetFPGA-public/wiki/NetFPGA-1G-CML-Ethernet-Interface-Loopback-Test" >Wiki</a></td> </tr> <tr> <td>Reference NIC</td> <td>CML / University of Cambridge</td> <td><a href="https://github.com/NetFPGA/NetFPGA-public/wiki/NetFPGA-1G-CML-Reference-NIC" >Wiki</a></td> </tr> <tr> <td>Reference Flash</td> <td>CML / University of Cambridge</td> <td><a href="https://github.com/NetFPGA/NetFPGA-public/wiki/NetFPGA-1G-CML-Reference-Flash" >Wiki</a></td> </tr> <tr> <td>Learning CAM Switch</td> <td>CML / University of Cambridge</td> <td><a href="https://github.com/NetFPGA/NetFPGA-public/wiki/NetFPGA-1G-CML-Learning-CAM-Switch" >Wiki</a></td> </tr> <tr> <td>Learning Switch (Lite)</td> <td>CML / University of Cambridge</td> <td><a href="https://github.com/NetFPGA/NetFPGA-public/wiki/NetFPGA-1G-CML-Learning-Switch-Lite" >Wiki</a></td> </tr> <tr> <td>Reference Router</td> <td>CML / University of Cambridge</td> <td><a href="https://github.com/NetFPGA/NetFPGA-public/wiki/NetFPGA-1G-CML-Reference-Router" >Wiki</a></td> </tr> </table> </div> </div> <br> <hr> <div id="accordion-CML4" class="accordion"> <div class="collapsed" data-toggle="collapse" href="#collapse-CML4"> <button class="card-title" ><h2>Resources  </h2></button> </div> <div id="collapse-CML4" class="collapse" data-parent="#accordion-CML4"> <br> <p class="FAQ">Where can I buy a NetFPGA 1G CML Platform?</p> <ul> <li>Check <a href="http://store.digilentinc.com/netfpga-1g-cml-kintex-7-fpga-development-board/" >here</a>.</li> </ul> <p class="FAQ">It seems that my board is broken, what should I do?</p> <ul> <li>Contact your <a href="http://www.digilentinc.com/contact.cfm" >suppliers</a>.</li> </ul> <p class="FAQ">What if I have Hardware problems with my board?</p> <ul> <li>Contact your <a href="http://www.digilentinc.com/contact.cfm" >suppliers</a>.</li> </ul> <p class="FAQ">What if I have Software problems with my board?</p> <ul> <li>Contact your <a href="https://cmlab.biz" >suppliers</a>.</li> </ul> <p class="FAQ">You can exchange your ideas and questions with the NetFPGA CML community <a href="https://lists.cam.ac.uk/mailman/listinfo/cl-netfpga-cml-beta" >here</a>.</p> <p class="FAQ">How can I get involved with the NetFPGA project?</p> <ul> <li>Register with the <a href="https://lists.cam.ac.uk/mailman/listinfo/cl-netfpga-cml-announce" >netfpga-cml-annouce mailing list</a> to receive NetFPGA project announcements.</li> <li>Become a <a href="http://www.facebook.com/home.php#/pages/NetFPGA/29922917839" >fan on Facebook</a>.</li> <li>Become a <a href="https://twitter.com/netfpga" >fan on Twitter</a>.</li> </ul> <p class="FAQ">How can I obtain the gateware and software package?</p> <li><a href="{% link CML-reg-form.html %}">Registration</a></li> <li><a href="https://github.com/NetFPGA/NetFPGA-public/wiki/Licensing" >NetFPGA-1G-CML license</a></li> <br> <p class="FAQ">Once you have used the NetFPGA, we hope that you will contribute to the project.</p> <br> <p class="FAQ">You can find our Wiki <a href="https://github.com/NetFPGA/netfpga/wiki" >here</a>.</p> </div> </div> <br> <hr> |
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