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nightlytestsuite/pyunit: StopWatch example: sync_Bits and sync_Bit drive the…
…ir port 'Output', so its mode is 'out'.
Entity sync_Bits, entity sync_Bit and component sync_Bit declared 'output : in', although both architectures assign
'Output'; GHDL rejects that on analysis (port "output" can't be assigned). The port map of the component instance
associated 'Input' twice ('Input => Output(i)'); it associates 'Output' now.
Co-Authored-By: Patrick Lehmann <[email protected]>
v6.0.0-rc.1candidate release 6.0.0-rc.1 v5.0.0-rc6Bump version to 5.0.0-rc6 PreviousNext
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