Issues

Issues

• Math operations on all-negative-range [su]fixed return zero-length vector for integer constants

  nickg/nvc#1754 · opened on Nov 11, 2026
  1

• Constrained array parameter indexed with the actual’s range when the subtype depends on a function-computed generic

  nickg/nvc#1752 · opened on Nov 9, 2026
  3

• Subprogram alias without a signature is accepted

  nickg/nvc#1751 · opened on Nov 8, 2026

• --cover-merge adds hits to the wrong items when elaborations differ

  nickg/nvc#1745 · opened on Nov 7, 2026

• Inconsistent and missing coverage items for if statements whose condition is constant because of a generic

  nickg/nvc#1744 · opened on Nov 7, 2026
  4

• -- coverage off is ignored for a when others choice inside a generate

  nickg/nvc#1743 · opened on Nov 7, 2026

• Coverage Merging is not producing the Union of coverage correctly

  nickg/nvc#1742 · opened on Nov 7, 2026

• Nested procedures with an empty signature in a generic package share one body

  nickg/nvc#1740 · opened on Nov 7, 2026

• Support Verilog named events

  nickg/nvc#1736 · opened on Nov 6, 2026

• Return value not checked against the function's constrained return subtype

  nickg/nvc#1728 · opened on Nov 5, 2026
  1

• a scalar out parameter bound to a shared variable is passed by reference

  nickg/nvc#1725 · opened on Nov 4, 2026
  1

• a relative external name inside a for-generate reads the first iteration's object in every iteration

  nickg/nvc#1724 · opened on Nov 4, 2026

• a function returning its array parameter returns the actual's own storage, so the call's result changes later

  nickg/nvc#1723 · opened on Nov 4, 2026
  1

• Interpreter keeps dead pointers alive: deallocated objects retained by stale registers (unbounded growth with linked lists)

  nickg/nvc#1688 · opened on Oct 13, 2026
  2

• Verilog - Hierarchical reference inside labeled generete

  nickg/nvc#1680 · opened on Oct 6, 2026
  1

• Verilog - MIN_TYP_MAX expression

  nickg/nvc#1677 · opened on Oct 6, 2026

• nvc --do creates always an empty work library

  nickg/nvc#1675 · opened on Oct 6, 2026
  8

• Compilation of Xilinx Microblaze

  nickg/nvc#1671 · opened on Oct 1, 2026
  1

• [BUG] VHDL-2019 conditional expressions break when adding parentheses

  nickg/nvc#1669 · opened on Sep 29, 2026
  4

• using expressions over ports as actuals to nested entity instantiations results in undefined values

  nickg/nvc#1662 · opened on Sep 19, 2026

• block rule in a coverage spec file only matches the nearest named scope, not the whole entity subtree

  nickg/nvc#1654 · opened on Sep 6, 2026
  1

• Assertion failed: error_count() > 0, file ../src/vlog/vlog-symtab.c, line 287

  nickg/nvc#1650 · opened on Aug 27, 2026

• *nvc --install* in Windows

  nickg/nvc#1646 · opened on Aug 24, 2026

• Mixed simulation question

  nickg/nvc#1642 · opened on Aug 14, 2026
  2

• Code coverage pragma bug

  nickg/nvc#1635 · opened on Aug 8, 2026