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GeezerVison is showing github.com — Add support for ARM GICv5 by sarah-walker-arm · Pull Request #11240 · tianocore/edk2 Conversation
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DescriptionAdd support for the ARM GICv5 interrupt controller. This pull request includes the changes to the ArmGicDxe driver, supporting ArmLib changes to detect GICv5 presence, and an update to the TimerDxe driver to support the GICv5 architected PPI numbers.
How This Was TestedBoot FVP VersatileExpress model with both GICv3 and GICv5 configurations. Confirmed boot to Linux with appropriate DTB. Integration InstructionsN/A
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There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. Aside from the comments that @leiflindholm has. Looks good to me.
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Before extending the GicV3Dxe driver with support for GICv5, make the driver AArch64-only to avoid the need for adding support to the 32-bit build, which would be rather pointless. Signed-off-by: Ard Biesheuvel <[email protected]> The AA64PFR2 system register is required to detect GICv5 support. Signed-off-by: Sarah Walker <[email protected]> Signed-off-by: Sarah Walker <[email protected]>
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Add initial driver support for GICv5. This initial driver supports Private Peripheral Interrupts (PPIs) and Shared Peripheral Interrupts (SPIs). Signed-off-by: Sarah Walker <[email protected]> [ardb: Merge v5 support into GicV3Dxe] Signed-off-by: Ard Biesheuvel <[email protected]> GICv5 uses a different ID scheme for interrupt numbers to previous GICs; the top bits indicate the type of interrupt (PPI/SPI/LPI). Update TimerDxe to use the new ID scheme for GICv5. As the timer PPIs are architected for GICv5 they should be the same on all GICv5 platforms. Signed-off-by: Sarah Walker <[email protected]>
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