Two AMD Ryzen 9000 series microprocessors with Zen 5 architecture
Zen 5 ("Nirvana")[1] is a microarchitecture for CPUs by AMD, shown on their roadmap in May 2022,[2] launched for mobile in July 2024 and for desktop in August 2024.[3] It is the successor to Zen 4 and is currently fabricated on TSMC's N4P process.[4] Zen 5 is also planned to be fabricated on the N3E process in the future.[5]
The Zen 5 microarchitecture powers Ryzen 9000 series desktop processors (codenamed "Granite Ridge"), Epyc 9005 server processors (codenamed "Turin"),[6] and Ryzen AI 300 thin and light mobile processors (codenamed "Strix Point").[7][8]
Background
Zen 5 was first officially mentioned during AMD's Ryzen Processors: One Year Later presentation on April 9, 2018.[9]
A roadmap shown during AMD's Financial Analyst Day on June 9, 2022 confirmed that Zen 5 and Zen 5c would be launching in 3nm and 4nm variants in 2024.[10] The earliest details on the Zen 5 architecture promised a "re-pipelined front end and wide issue" with "integrated AI and Machine Learning optimizations".[10]
During AMD's Q4 2023 earnings call on January 30, 2024, AMD CEO Lisa Su stated that Zen 5 products would be "coming in the second half of the year".[11]
Architecture
Die-Shot of an AMD Ryzen 5 9600X with a Zen 5 microarchitecture
Zen 5 is a ground-up redesign of Zen 4 with a wider front-end, increased floating-point throughput, and more-accurate branch prediction.[12]
Fabrication process
Zen 5 was designed with both 4nm and 3nm processes in mind. This acted as an insurance policy for AMD in the event that TSMC's mass production of its N3 nodes were to face delays, significant wafer defect issues, or capacity issues. One industry analyst estimated early N3 wafer yields to be at 55% while others estimated yields to be similar to those of N5 at between 60-80%.[13][14] Additionally, Apple, as TSMC's largest customer, gets priority access to the latest process nodes. In 2022, Apple was responsible for 23% of TSMC's $72 billion in total revenue.[15] After N3 began ramping at the end of 2022, Apple bought up the entirety of TSMC's early N3B wafer production capacity to fabricate their A17 and M3 SoCs.[16] Zen 5 desktop and server processors continue to use the N6 node for the I/O die fabrication.[17]
Zen 5 Core Complex Dies (CCDs) are fabricated on TSMC's N4X node which is intended to accommodate higher frequencies for high-performance computing (HPC) applications.[18] Zen 4-based mobile processors were fabricated on the N4P node which is targeted more toward power efficiency. N4X maintains IP compatibility with N4P and offers a 6% frequency gain over N4P at the same power but comes with the trade-off of moderate leakage.[19] Compared to the N5 node used to produce Zen 4 CCDs, N4X can enable up to 15% higher frequencies while running at 1.2V.[20]
The Zen 5 CCD, codenamed "Eldora", has a die size of 70.6mm2, a 0.5% reduction in area from Zen 4's 71mm2 CCD while achieving a 28% increase in transistor density due to the N4X process node.[21] Zen 5's CCD contains 8.315 billion transistors compared to the Zen 4 CCD's 6.5 billion transistors.[22] One Zen 5 core is larger than one Zen 4 core, but the CCD has been reduced via shrinking the L3 cache. The monolithic die used by "Strix Point" mobile processors, fabricated on TSMC's lower power N4P node, measures 232.5mm2 in area.[21]
Front end
Branch prediction
Zen 5's changes to branch prediction are the most significant divergence from any previous Zen microarchitecture. The branch predictor in a core tries to predict the outcome when there are diverging code paths.
Zen 5's branch predictor is able to operate two-ahead where it can predict up to two branches per clock cycle. Previous architectures were limited to one branch instruction per clock cycle, limiting the instruction-fetch throughput of branch-heavy programs.[23] Two-ahead branch predictors have been discussed in academic research dating back to André Seznec et al.'s 1996 paper "Multiple-block ahead branch predictors".[24] 28 years after it was first proposed in academic research, AMD's Zen 5 architecture became the first microarchitecture to fully implement two-ahead branch prediction.[4] Increased data prefetching assists the branch predictor.[4]
Execution engines
Integer units
Zen 5 contains six Arithmetic Logic Units (ALUs), up from four ALUs in prior Zen architectures. A greater number of ALUs that handle common integer operations can increase per-cycle scalar integer throughput by 50%.[25]
Vector engines and instructions
The vector engine in Zen 5 features four floating-point pipes compared to three pipes in Zen 4. Zen 4 introduced AVX-512 instructions. AVX-512 capabilities have been expanded with Zen 5 with a doubling of the floating-point pipe width to a native 512-bit floating-point datapath. The AVX-512 datapath is configurable depending on the product. Ryzen 9000 series desktop processors and EPYC 9005 server processors feature the full 512-bit datapath, but Ryzen AI 300/400 mobile processors feature a 256-bit datapath to reduce power consumption. AVX-512 instructions have been extended with the VP2INTERSECT extension, in addition to 256-bit AVX-VNNI. Additionally, there is greater bfloat16 throughput.[4]
Cache
L1
The wider front end in the Zen 5 architecture necessitates larger caches and higher memory bandwidth in order to keep the cores fed with data. The L1 cache per core is increased from 64KB to 80KB per core. The L1 instruction cache remains the same at 32KB but the L1 data cache is increased from 32KB to 48KB per core. Furthermore, the bandwidth of the L1 data cache for 512-bit floating-point unit pipes has also been doubled. The L1 data cache's associativity has increased from 8-way to 12-way in order to accommodate its larger size.[4]
L2
The L2 cache remains at 1MB but its associativity has increased from 8-way to 16-way. Zen 5 also has a doubled L2 cache bandwidth of 64 bytes per clock.[4]
Cache
Zen 4
Zen 5
L1 (Data)
Size
32KB
48KB
Associativity
8-way
12-way
Bandwidth
32B/clk
64B/clk
L1 (In- struc- tions)
Size
32KB
32KB
Associativity
8-way
8-way
Bandwidth
64B/clk
64B/clk
L2
Size
1MB
1MB
Associativity
8-way
16-way
Bandwidth
32B/clk
64B/clk
L3
Size
32MB
32MB
Associativity
16-way
16-way
Bandwidth
32B/clk Read 16B/clk Write
32B/clk Read 16B/clk Write
L3
The L3 cache is filled from L2 cache victims and in-flight misses. Latency for accessing the L3 cache has been reduced by 3.5 cycles.[26] A Zen 5 Core Complex Die (CCD) contains 32MB of L3 cache shared between the 8 cores. In Zen 5 3D V-Cache CCDs, a piece of silicon containing 64MB of extra L3 cache is placed under the cores rather than on top like in prior generations for a total of 96MB.[27] This allows for increased core frequency compared to previous generation 3D V-Cache implementations which were sensitive to higher voltages. The Zen 5-based Ryzen 7 9800X3D has a 500MHz increased base frequency over the Zen 4-based Ryzen 7 7800X3D and allows overclocking for the first time.[28]
Ryzen AI 300 APUs, codenamed "Strix Point", features 24MB of total L3 cache which is split into two separate cache arrays. 16MB of dedicated L3 cache is shared by the 4 Zen 5 cores and 8MB is shared by the 8 Zen 5c cores.[29] Zen 5c cores are not able to access the 16MB L3 cache array and vice versa.[30]
Other changes
Other features and changes in the Zen 5 architecture, compared to Zen 4, include:
Memory speeds up to DDR5-5600 (From DDR5-5200) and LPDDR5X-7500 are officially supported.[31]
AMD announced an initial lineup of four models of Ryzen 9000 processors on June 3, 2024, including one Ryzen 5, one Ryzen 7 and two Ryzen 9 models. Manufactured on a 4nm process, the processors feature between 6 and 16 cores.[33] Ryzen 9000 processors were released in August 2024.[4]
In May 2025 four of these processors were also released in the 4005 range of the EPYC brand,[34] with the 4585PX corresponding to the 9950X3D, the 4565P to the 9950X, the 4345P to the 9700X, and the 4245P to the 9600. Two EPYC 4005 parts, both 65W, have no direct Ryzen 9000 series equivalent: the EPYC 4465P with 12 cores at 3.4GHz, and the 4545P with sixteen cores at 3.0GHz.[34]
In April 2026, AMD launches the Ryzen 9 9950X3D2 Dual Edition with a 200W TDP. This marks the return of 200W TDP in its consumer desktop CPU lineup for the first time since the 220W AMD FX-9590.
All the CPUs support DDR5-5600 RAM in dual-channel mode in 2x1R and 2x2R configuration, but only DDR5-3600 for 4x1R and 4x2R.
All the CPUs support 28 PCIe 5.0 lanes. 4 of the lanes are reserved as link to the chipset.
Includes integrated RDNA 2 GPU with 2 CUs and base and boost clock speeds of 0.4 GHz and 2.2 GHz, respectively. Models with "F" suffixes are without iGPUs.
L1 cache: 80 KB (48 KB data + 32 KB instruction) per core.
L2 cache: 1 MB per core.
Models with an "X3D" suffix include 2nd-generation 3D V-Cache in the form of a 64 MB cache die, which augments the L3 cache of one CCD.[35]
Models with an "X3D2" suffix or branded as "Dual Edition" include 2nd-generation 3D V-Cache in the form of two 64 MB cache dies (totaling to 128 MB), one die per CCD, which augment the L3 cache of their respective CCD.[36]
Fabrication process: TSMCN4XFinFET (N6 FinFET for the I/O die).
AMD announced the Threadripper 9000 series of high-end desktop processors at Computex 2025, which released on July 30, 2025. These processors succeed the Zen 4 "Storm Peak" lineup and feature up to 96 Zen 5 cores. The processors come in two variants—the consumer "Threadripper" models and the more expensive workstation "Threadripper PRO" variants, which support more memory channels and PCIe lanes.[48]
Common features of Ryzen 9000 HEDT/workstation CPUs:
Threadripper CPUs support DDR5-6400 in quad-channel mode while Threadripper PRO CPUs support DDR5-6400 in octa-channel mode with ECC support.
L1 cache: 80KB (48KB data + 32KB instruction) per core.
L2 cache: 1MB per core.
Threadripper CPUs support 80 PCIe 5.0 lanes (4 of which runs PCIe 4.0 mode to the chipset; and remaining are usually running as 48 PCIe 5.0 lanes plus 24 PCIe 4.0 lanes), while Threadripper PRO CPUs support 128 PCIe 5.0 lanes (4 of which runs in PCIe 4.0 mode to the chipset), and extra 8 PCIe 3.0 lanes. Some lanes support alternative mode of running SATA3.
Threadripper 9000 processors officially support up to 6400 MT/s DDR5 memory, a significant increase from 5200 MT/s in the previous generation.[50]
AI 400 Series
AMD announced an initial lineup of 6 models of Ryzen AI 400 processors on March 2, 2026, including two Ryzen 5 and one Ryzen 7 models. Manufactured on a 4 nm process, the processors feature between 6 and 8 cores.[51]
Common features of Ryzen AI 400 desktop APUs:[52][53]
The Ryzen AI 300 series of notebook processors was announced on June 3, 2024. Codenamed Strix Point (for the high performance Ryzen AI 9 300 series) & Krackan Point (for the mid-range Ryzen AI 5 and 7 300 series), these processors are named under a new model numbering system similar to Intel's Core and Core Ultra model numbering. Strix Point features a 3rd-gen Ryzen AI engine based on XDNA 2, providing up to 50 TOPS of neural processing unit performance. The integrated graphics is upgraded to RDNA 3.5, and top-end models have 16 CUs of GPU and 12 cores of CPU, an increase from the maximum of 8 CPU cores on previous-generation Ryzen ultra-thin mobile processors.[54] Notebooks featuring Ryzen AI 300 series processors were released on July 17, 2024.[55]
12345Model also available as "H" version as H 430, H 435, H PRO 435, H PRO 440, H 445, H PRO 445, H 450, H PRO 450, H 465, and H PRO 465, but lacks support for AMD EXPO and FreeSync technologies.
Strix Halo
Strix Halo represented a major departure of previous multi-chiplet mobile processors. Strix Halo's CCD is actually not the same type of CCD used on regular Zen 5 desktop processors. Instead it features a unique "sea of wires" interconnect that replaces the previous infinity fabric. This change allowed for greater power efficiency but also greater design complexity. This type of interconnect is rumored to be on Zen 6, the next generation of AMD CPU microarchitecture.[62][63]
Alongside Granite Ridge desktop and Strix Point mobile processors, the Epyc 9005 series of high-performance server processors, codenamed Turin, were also announced at Computex on June 3, 2024. It uses the same SP5 socket as the previous Epyc 9004 series processors, and packs up to 128 cores and 256 threads on the top-end model. Turin is built on a TSMC 4 nm process.[67]
Common features of EPYC 9005 server processors:
A variant of Epyc 9005 using Zen 5c ("Prometheus") cores was also shown off at Computex. It features a maximum of 192 cores and 384 threads, and is manufactured on a 3 nm process.[67]
Common features of EPYC Dense 9000 server processers:
Zen 5c ("Prometheus") is a compact variant of the Zen 5 ("Nirvana")[1] core, primarily targeted at hyperscale cloud compute server customers.[68] It succeeds the Zen 4c ("Dionysus") core.
See also
Arrow Lake - a competing x86 CPU lineup from Intel for Granite Ridge, Fire Range, and the Ryzen AI 300 series
Lunar Lake - a competing mobile x86 CPU lineup for Ryzen AI 300 series
Granite Rapids - a competing x86 CPU lineup for Turin Classic
Sierra Forest - a competing x86 CPU lineup for Turin Dense
↑Seznec, André; Jourdan, Stéphan; Sainrat, Pascal; Michaud, Pierre (1996). "Multiple-block ahead branch predictors". Proceedings of the seventh international conference on Architectural support for programming languages and operating systems. pp.116–127. doi:10.1145/237090.237169. ISBN0-89791-767-7. Archived from the original on September 16, 2024. Retrieved September 16, 2024.
↑Lam, Chester (October 8, 2023). "Zen 5's Leaked Slides". Chips and Cheese. Retrieved June 3, 2024.
↑"AMD 3D V-Cache™ Technology". AMD. 2026. Archived from the original on October 7, 2025. Retrieved January 14, 2026. the AMD Ryzen™ 9000X3D Series [...] 2nd Gen AMD 3D V-Cache™ Technology [...] 64MB L3 Cache Die
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