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FV Utilites Functional Verification Utilities

FVUtils - Functional Verification Utilities

FVUtils is a collection of open-source tools designed for functional verification engineers and developers. From constrained-random stimulus generation to coverage analysis, transaction tracing to HDL integration, FVUtils provides modern, Python-centric solutions for today's verification challenges.

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User-Facing Tools

Production-ready tools for verification engineers working on design verification, stimulus generation, and coverage analysis.

PyVSC

Python Verification Stimulus and Coverage

constrained-random coverage cocotb

A Python library for verification stimulus and coverage, bringing SystemVerilog-style constrained-random and functional coverage capabilities to Python-based verification environments.

Documentation GitHub PyPI

PyHDL-IF

Python Interface for HDL Simulators

Seamless integration between Python and SystemVerilog. Run async pytest tests from SystemVerilog testbenches, call SV functions from Python, and pass structured data using ctypes.Structure. Perfect for modern Python-based verification flows.

Start Python behavior from SystemVerilog/UVM
Run async pytest tests from SV testbenches
Pass structured data with ctypes.Structure

Documentation GitHub

PyUCIS

Python API to UCIS Coverage Data

UCIS coverage Accellera

Python API for reading and manipulating Unified Coverage Interoperability Standard (UCIS) data. Enables programmatic access to coverage databases from any UCIS-compliant tool.

Documentation GitHub PyPI

PyUCIS Viewer

Qt-based UCIS Coverage Viewer

A desktop application for viewing and analyzing UCIS coverage data. Browse coverage hierarchies, analyze metrics, and visualize results from any UCIS-compliant simulator.

Documentation GitHub

IVPM

IP and Verification Package Manager

A Python and Git-centric package manager for managing external project dependencies. Originally designed for hardware design, it works with any Git-based project.

Documentation GitHub

PyWellen MCP

Waveform Analysis via Model Context Protocol

MCP server enabling LLM agents to analyze digital waveform files (VCD, FST, GHW) using natural language queries. Features 35+ tools for signal analysis, pattern detection, and waveform export.

Multi-format waveform support (VCD, FST, GHW, LXT)
Natural language queries for signal analysis
GTKWave, Verdi, Simvision integration

Documentation GitHub

DV Transaction Trace

Transaction Logging with Perfetto

SystemVerilog and Python bindings for writing transactional data to Perfetto traces. Visualize transaction-level activity from your verification environment using Google's Perfetto UI.

SystemVerilog and Python APIs
UVM recorder integration
Beautiful Perfetto timeline visualization

GitHub

Developer-Focused Tools

Infrastructure and build tools for developers creating verification environments and EDA workflows.

QEMU Model Loader

Dynamic Device Model Loading for QEMU

Research and documentation for loading QEMU device models as dynamically loaded shared libraries. Includes working examples, design documentation, and best practices for extending QEMU without recompilation.

Complete technical analysis of QEMU's device architecture
Working examples with source code
Security considerations and best practices

GitHub

SVDep

SystemVerilog Dependency Management

A dependency management tool for SystemVerilog that tracks when files have been modified, enabling incremental builds and optimized compilation workflows.

GitHub

FLTools

EDA Filelist Utilities

Utilities for parsing and manipulating EDA tool filelists. Handles relative paths, comments, duplicate detection, and common filelist formats used across the EDA ecosystem.

Parse EDA tool filelists
Resolve relative paths and working directories
Detect duplicate filelist inclusion

GitHub