Pinned Loading

1. pulp-platform/TeraNoC pulp-platform/TeraNoC Public

   An open-source hybrid Mesh–Crossbar NoC for scalable, low-latency shared-L1-memory clusters with thousands of cores.

   C 44 12

2. pulp-platform/pulp-c910 pulp-platform/pulp-c910 Public

   PULP C910, a superscalar out-of-order RISC-V core adapted from T-Head's openC910 (Alibaba Group) and integrated into the PULP ecosystem with several modifications.

   SystemVerilog 22 9

3. OpenExSys_CoherentCache OpenExSys_CoherentCache Public

   OpenExSys_CoherentCache a directory-based MESI protocol coherent cache IP.

   SystemVerilog 26

4. OpenExSys_NoC OpenExSys_NoC Public

   OpenExSys_NoC a mesh-based network on chip IP.

   SystemVerilog 21

5. APD APD Public

   A 64-bit dual-issue out-of-order RISC-V processor, develop with systemverilog. It has 2 level PAg branch predictor, 2-level cache system, mmu, csr, precise exception support, reorder buffer

   C 5

6. ORV32s ORV32s Public

   A 2-stage pipeline RISC-V scalar core for embedded and low-power controllers.

   C 4