Aruna Jayasena Archfx

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Assistant Professor | Research Engineer | Automotive Enthusiast | PhD @ UF

Achievements

archfx/README.md

I am an Assistant Professor and a Systems Engineer. My interests lie at the thin intersection of Electronics Engineering and Computer Engineering. ✌️

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FPGA-stereo-Camera-Basys3 FPGA-stereo-Camera-Basys3 Public

Integration of two camera 📷 modules to Basys 3 FPGA

Verilog 48 9
sweetRV sweetRV Public

sweetRV 🧁 is a SoC with a minimal RISC-V processor with firmware for IceSugar-Nano FPGA

C++ 8 2
RTK-NTRIP-RTCM RTK-NTRIP-RTCM Public

Contains program to Send RTCM3 📡 data to Hosted NTRIP server and fetch NTRIP data and display on another rover. Real time kinematic supported base and rover (Ublox-M8P) GPS units are required.

Python 29 6
duo-de duo-de Public

Surface Duo Dual Experience ( 🍰 AOSP | Android 16 | DUO1 | DUO2 )

Shell 370 14
FPGA-DepthMap-Basys3 FPGA-DepthMap-Basys3 Public

Realtime depth map 🏞️ generation using SSD algorithm on low end Basys 3 FPGA. Support 320x240 and 160x120 resolutions.

VHDL 23 5
ice40lib ice40lib Public

Peripheral library 📚 for open source FPGAs based on iCE40. (Configured for ICESugar-Nano)

Verilog 8 2

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