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@Herrtian
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Tian Teng Herrtian

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Student in Germany
12 followers · 59 following
  • 14:17 (UTC +01:00)
  • in/tianteng

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Achievement: Pair ExtraordinaireAchievement: Pull Sharkx2Achievement: StarstruckAchievement: Quickdraw
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herrtian/README.md

Hi, I'm Tian Teng

Engineering student based in Germany.

I work across wireless communication, cybersecurity, hardware design, backend systems, and DevOps tooling. Recently I have also been spending more time on TypeScript, Node.js, and open-source tooling around the SAP ecosystem.

What I Work On

  • Wireless Communication - SDR, channel estimation, signal processing with MATLAB and Python
  • FPGA & Digital Design - RTL development in SystemVerilog, hardware-software co-design
  • Cybersecurity - network security research, protocol analysis
  • Backend Engineering - APIs, services, automation, and developer infrastructure
  • DevOps & CI/CD - GitHub Actions, Docker, Linux, testing pipelines, release automation, and build tooling
  • TypeScript & Node.js - libraries, CLIs, test tooling, and package maintenance
  • SAP Ecosystem - UI5/Fiori tooling, CAP/CDS, OData, SAP HANA integrations, Cloud SDK, MTA, and SAP open-source projects

Tech Stack

MATLAB Python C/C++ SystemVerilog TypeScript Node.js Cython FPGA GNU Radio UHD Linux Docker GitHub Actions CI/CD Kubernetes SAP UI5 CAP CDS OData SAP HANA SAP Cloud SDK MTA

Highlights

  • Contributor to UHD, the open-source driver and framework for Ettus USRP software-defined radios
  • Co-maintainer of PicoScenes-Python-Toolbox, parsing CSI data for WiFi sensing research
  • Active open-source contributor across Python, Go, TypeScript, documentation, DevOps tooling, and SAP-related projects

"The best way to understand a system is to build one."

Pinned Loading

  1. wifisensing/PicoScenes-Python-Toolbox wifisensing/PicoScenes-Python-Toolbox Public

    The Python toolbox to parse the .csi files generated by PicoScenes.

    Cython 43 17

  2. uhd uhd Public

    Forked from EttusResearch/uhd

    The USRP™ Hardware Driver Repository

    Verilog

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