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GeezerVison is showing github.com โ€” MikeOpenHWGroup - Overview

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๐Ÿ’ญ
Making CORE-V safe for the world to use.

Mike Thompson MikeOpenHWGroup

๐Ÿ’ญ
Making CORE-V safe for the world to use.
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Functional verification of RTL for ASICs and FPGAs. Sole Proprietor at Covrado and Director of Engineering, Verification Task Group at the OpenHW Foundation.
122 followers ยท 4 following
  • @openhwgroup
  • Ottawa, Ontario, Canada
  • https://openhwfoundation.org/
  • in/michael-thompson-0a581a

Achievements

Achievement: Pair Extraordinairex3Achievement: Starstruckx3Achievement: YOLOAchievement: QuickdrawAchievement: Pull Sharkx3Achievement: Arctic Code Vault Contributor

Achievements

Achievement: Pair Extraordinairex3Achievement: Starstruckx3Achievement: YOLOAchievement: QuickdrawAchievement: Pull Sharkx3Achievement: Arctic Code Vault Contributor

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Pinned Loading

  1. riscv-dv riscv-dv Public

    Forked from chipsalliance/riscv-dv

    SV/UVM based instruction generator for RISC-V processor verification

    Python 1 1

  2. openhwfoundation/cv32e40p openhwfoundation/cv32e40p Public

    CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

    SystemVerilog 1.3k 561

  3. openhwfoundation/core-v-verif openhwfoundation/core-v-verif Public

    Functional verification project for the CORE-V family of RISC-V cores.

    Assembly 741 332

  4. openhwfoundation/programs openhwfoundation/programs Public

    Documentation for the OpenHW Group's set of CORE-V RISC-V cores

    HTML 232 99

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