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GeezerVison is showing github.com β€” RISC-KC

README.md

RISC-KC

cpu(3)

RISC-KC Icon logo. Cpu icons created by Freepik - Flaticon, modified.

image Signal Level block diagram of RV32I46F_5SP_MMIO Processor architecture from basic_RV32s.

What is RISC-KC? 🌟

  • RISC-KC is a RISC-V Processor Development organization
    • Named after members Last name; Hyun Woo Kang and ChoiCube84.
  • Our goal is to make full open-source General Purpose RISC-V Processor that can actually run modern OS such as linux.
    • Not only FPGA, but also as a real chip in future.

RISC-KC Roadmap πŸ“‹

  • RV32I basic_RV32s πŸ“Œ
    • RV32I single-cycle (2025.06.01.)βœ…
    • RV32I 5-stage pipeline (2025.06.20.)βœ…
  • RV64IMA ima_make_RV64 πŸ“Œ
    • RV64I 5-stage pipeline (2026.01.06.)βœ…
    • RV64IM 5-stage pipeline (2026.01.17.)βœ…
    • RV64IM 6-stage pipeline (2026.01.27.)βœ…
    • RV64IM 7-stage pipeline with 100MHz Clock speed <--- currently working πŸ› οΈ
    • RV64IM 7SP 100MHz with Cache structure
    • RV64IM 7SP 100MHz Cached with multiple core structure
    • RV64IMA 7SP 100MHz Cached multicore architecture
  • RV64IMAFD
  • RV64G !!
  • ...
  • RVA23...

RISC-KC History πŸ“–

  • RISC-KC was organized by starting basic_RV32s in 2025.12.10.
    • When our members were serving in the military in South Korea. 711ν†΅μ‹ λŒ€λŒ€
  • We are advancing our works to make it possible to support RV64G with modern processor architectures.
  • Development Environment
    • Digilent Nexys Video FPGA (Artix-7 XC7A200T)
    • Visual Studio Code
    • AMD Xilinx Vivado
    • Icarus Verilog (iverilog)
    • Surfer Project (waveform viewer)
    • Teraterm
    • GTKterm
    • draw.io
    • Windows 10 / Linux Ubuntu 24.04 LTS

Members

  • Hyun Woo Kang and ChoiCube84

Popular repositories Loading

  1. basic_rv32s basic_rv32s Public

    πŸŽ“ Instructional RISC-V processor design framework: single-cycle to 5-stage pipeline with FPGA verification and complete learning guidelines! A RISC-V CPU design guideline.

    Verilog 113 11

  2. ima_make_rv64 ima_make_rv64 Public

    I'ma make rv64 cpu.

    Verilog 3

  3. .github .github Public

    RISC-KC organization README repository

Repositories

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  • ima_make_rv64 Public

    I'ma make rv64 cpu.

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    RISC-KC/ima_make_rv64's past year of commit activity
    Verilog 3 MIT 0 0 0 Updated Feb 19, 2026
  • basic_rv32s Public

    πŸŽ“ Instructional RISC-V processor design framework: single-cycle to 5-stage pipeline with FPGA verification and complete learning guidelines! A RISC-V CPU design guideline.

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    RISC-KC/basic_rv32s's past year of commit activity
    Verilog 113 MIT 11 0 0 Updated Feb 2, 2026
  • .github Public

    RISC-KC organization README repository

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    RISC-KC/.github's past year of commit activity
    0 0 0 0 Updated Jan 28, 2026

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