Pinned Loading

1. SARV SARV Public

   SARV A Risc-V

   Verilog 13

2. SARV-SoC SARV-SoC Public

   An open source, modular 32-bit RISC-V System-on-Chip (SoC) built around the SARV processor core, featuring caches, ACLINT, PLIC, UART, and GPIO.

   SystemVerilog 3

3. PLIC PLIC Public

   RISC-V Platform-Level Interrupt Controller

   SystemVerilog 5

4. ACLINT ACLINT Public

   ACLINT (Advanced Core Local Interrupt Controller)

   SystemVerilog 6

5. SARV-Cache SARV-Cache Public

   Configurable instruction and data cache subsystem

   SystemVerilog 3

6. UART UART Public

   A parametrizable, modular UART with FIFO buffers, even parity, and interrupt support.

   SystemVerilog 3