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A FPGA friendly 32 bit RISC-V CPU implementation
Assembly
3.3k
522
A basic SpinalHDL project
Scala
101
72
Labs to learn SpinalHDL
Scala
160
44
The sources of the online SpinalHDL doc
Python
33
69
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Showing 10 of 42 repositories
VexiiRiscv
Public
Like VexRiscv, but, Harder, Better, Faster, Stronger
SpinalHDL/VexiiRiscv's past year of commit activity
Scala
271
MIT
74
36
5
Updated Oct 31, 2026
SpinalHDL/SpinalDoc-RTD's past year of commit activity
SpinalHDL/SpinalHDL's past year of commit activity
SpinalHDL/riscv-isa-sim's past year of commit activity
SpinalHDL/NaxSoftware's past year of commit activity
C
13
10
1
2
Updated Oct 16, 2026
VexRiscv
Public
A FPGA friendly 32 bit RISC-V CPU implementation
SpinalHDL/VexRiscv's past year of commit activity
rvls
Public
RISCV lock-step checker based on Spike
SpinalHDL/rvls's past year of commit activity
C++
16
10
5
2
Updated Sep 20, 2026
SpinalHDL/VexiiRiscv-RTD's past year of commit activity
Python
5
CC0-1.0
6
0
5
Updated Aug 20, 2026
SpinalHDL/docker's past year of commit activity
Dockerfile
3
7
1
1
Updated Mar 1, 2026
SpinalHDL/NaxRiscv's past year of commit activity
Scala
329
MIT
52
62
0
Updated Jan 23, 2026