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Forked from VLSI-EDA/PoC
IP Core Library - Published and maintained by the Open Source VHDL Group
VHDL
99
10
A VHDL Core Library.
18
2
Interface definitions for VHDL-2019.
VHDL
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5
An abstract language model of VHDL written in Python.
Python
66
18
A Sphinx domain providing VHDL language support.
Python
21
5
Tests to evaluate the support of VHDL 2008 and VHDL 2019 features
VHDL
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Showing 10 of 21 repositories
VHDLDomain
Public
A Sphinx domain providing VHDL language support.
VHDL/VHDLDomain's past year of commit activity
Python
21
5
2
1
Updated Nov 12, 2026
pyVHDLModel
Public
An abstract language model of VHDL written in Python.
VHDL/pyVHDLModel's past year of commit activity
Python
66
18
8
0
Updated Nov 10, 2026
PoC
Public
Forked from
VLSI-EDA/PoC
IP Core Library - Published and maintained by the Open Source VHDL Group
VHDL/PoC's past year of commit activity
OSVVM-Scripts
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Forked from
OSVVM/OSVVM-Scripts
OSVVM project simulation scripts. Scripts are tedious. These scripts simplify the steps to compile your project for simulation
VHDL/OSVVM-Scripts's past year of commit activity
Tcl
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26
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0
Updated Nov 3, 2026
news
Public
VHDL related news.
VHDL/news's past year of commit activity
Python
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31
0
Updated Nov 3, 2026
OSVVM
Public
Forked from
OSVVM/OSVVM
OSVVM Utility Library: AlertLogPkg, CoveragePkg, RandomPkg, ScoreboardGenericPkg, MemoryPkg, TbUtilPkg, TranscriptPkg, ...
VHDL/OSVVM's past year of commit activity
VHDL
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75
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Updated Oct 25, 2026
Synchronize
Public
Auto Synchronize forked repositories.
VHDL/Synchronize's past year of commit activity
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Updated Oct 22, 2026
OSVVM-AXI4
Public
Forked from
OSVVM/AXI4
AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components
VHDL/OSVVM-AXI4's past year of commit activity
VHDL
1
28
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0
Updated Oct 22, 2026
OSVVM-Common
Public
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OSVVM/OSVVM-Common
Packages that implement OSVVM's model independent transactions and other shared verification component support packages. Required for all OSVVM verification components. AddressBusTransactionPkg - AXI, AxiLite, ... StreamTransactionPkg - AxiStream, UART, ...
VHDL/OSVVM-Common's past year of commit activity
VHDL
0
11
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0
Updated Oct 22, 2026
OSVVM-UART
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Forked from
OSVVM/UART
OSVVM UART Verification Components. Uart Transmitter with error injection for parity, stop, and break errors. UART Receiver verification component with error handling for parity, stop, and break errors.
VHDL/OSVVM-UART's past year of commit activity
VHDL
0
12
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0
Updated Sep 13, 2026
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