GeezerVison is showing github.com — nelsoncsc - Overview
- Hi, I’m Nelson Campos, a Staff Digital Design Engineer working with Digital Signal Processors at AMD in Edinburgh.
- Previously, I was a Senior Hardware Hardware Design Engineer working with Image Signal Processors at ARM in Manchester.
- I hold a BSc and MSc in EE and a PhD in CS.
- I’m interested in Digital Hardware Design and Verification, Digital Signal Processing, Vision Systems and Computer Arithmetic.
- 📫 You can reach me on Linkedin: https://linkedin.com/in/nelsoncsc
- 🌎 My personal blog: https://sistenix.com
- Fast Generation of Custom Floating-Point Spatial Filters on FPGAs
Nelson Campos, Eran Edirisinghe, Slava Chesnokov, Daniel Larkin.
IEEE Access 2024 arXiv pre-print 2024
- Framework for rapid hardware prototyping using custom floating-point arithmetic
Nelson Campos' PhD Thesis.
Loughborough University, United Kingdom.
- FPGA Implementation of a Custom Floating-Point Library
Nelson Campos, Eran Edirisinghe, Shaheen Fatima, Slava Chesnokov, Alexis Lluis
Intellisys 2022, Springer, Cham.
- FPGA Implementation of Custom Floating-Point Logarithm and Division
Nelson Campos, Slava Chesnokov, Eran Edirisinghe, Alexis Lluis
ARC 2021, Springer, Cham.
- Uma metodologia de projeto e validação de sistemas de detecção de faces
Nelson Campos' MSc Thesis (in Portuguese).
Universidade Federal de Campina Grande, Brazil.
- A Framework for Design and Validation of Face Detection Systems
Nelson Campos, Heron Monteiro, Alisson Brito, Antonio M. N. Lima, Elmar Melcher,
Marcos Morais
IEEE CHILECON 2017, Pucón, Chile.
- Energy Consumption Measurement of an FPGA Full-HD Video Processing Platform
Heron A. Monteiro, Nelson C. S. Campos, Jozias P. Oliveira, Antonio Marcus N. Lima,
Alisson V. Brito, Elmar U. K. Melcher
WCAS 2017, Fortaleza, Brazil.
- A 4-MHz parameterized Logarithm-Square Root IP-Core
Nelson Campos, Roberto Costa, Elton Costa, Gutemberg Junior, Elmar Melcher
IPSOC 2016, Grenoble, France.
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SystemVerilog AXI verification library and video-DMA IP: AXI4/Lite/Stream BFMs, triple-buffer VDMA, and multi-tap temporal VDMA with byte-exact real-image round-trip tests. Verilator · Yosys · Dock…
SystemVerilog
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A Framework for Design and Verification of Image Processing Applications using UVM
SystemVerilog
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A simple UVM example with DPI
SystemVerilog
48
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Reusable image processing modules in SystemVerilog
SystemVerilog
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