Hey, I'm partialHuman

Hi, I'm an electronics student who likes designing digital circuits and getting them running on real FPGA boards. I write Verilog for fun, build small things with TypeScript and Node.js when I want a change, and spend a suspicious amount of time making my Windows & Linux setup look better than it needs to.

Hardware by training, software by curiosity.

🛠️ Hardware design, simulation and on-board testing
🐧 Linux, GNOME Shell tweaks and VS Code extensions
🎮 Steam games, mostly to recover from debugging
☕ Powered by coffee, music and a suspicious number of retries
📈 One commit closer to competent

If you want to talk hardware, open source or why my testbench passed but the board didn't, say hi.

Known issues: sleep, merge conflicts, and "it works on my board."

🖥️ Languages & Core

🔧 VLSI & Hardware	🐧 Operating Systems

🤖 Embedded & Vision	☁️ Cloud & DevOps

📊 Data & ML	🧰 Dev Tools

🛡️ Networking & Security

See all repositories →

Quest	Stack	Status
FlexRISC16 _{5-stage pipelined 16-bit CPU}
Edge-AI Surveillance _{FPGA partial reconfiguration}
ProjectTree _{project tree and Mermaid generator}
Music Flyout _{GNOME Shell music controller}

github stats streak stats

most used languages

3D contribution skyline

_{Late nights}

_Fuel

_Music

📬 On the clock, find me here		🎮 Off the clock, find me here

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Hey, I'm partialHuman

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