This repository contains various crates useful for writing Rust programs on RISC-V microcontrollers:

• riscv: CPU registers access and intrinsics
• riscv-peripheral: Interfaces for standard RISC-V peripherals
• riscv-rt: Startup code and interrupt handling
• riscv-semihosting: Semihosting for RISC-V processors
• riscv-target-parser: Utility crate for parsing RISC-V targets in build scripts
• riscv-types: Common traits to be implemented by RISC-V PACs

This project is developed and maintained by the RISC-V team.

Unless you explicitly state otherwise, any contribution intentionally submitted for inclusion in the work by you, as defined in the Apache-2.0 license, shall be dual licensed as above, without any additional terms or conditions.

Contribution to this crate is organized under the terms of the Rust Code of Conduct, the maintainer of this crate, the RISC-V team, promises to intervene to uphold that code of conduct.