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GeezerVison is showing github.com — GitHub - scriptographers/CS254-Assignment-4: Assignment 4, Digital Logic Design Lab, Spring 2021, IIT Bombay

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NameName
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Q1
Q1
 
 
Q2
Q2
 
 
.gitignore
.gitignore
 
 
190100044_190100055_Lab4.zip
190100044_190100055_Lab4.zip
 
 
PS.pdf
PS.pdf
 
 
README.txt
README.txt
 
 

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CS 254: Assignment 4

Team Members:
1. Devansh Jain  (190100044)
2. Harshit Varma (190100055)

File Descriptions:

Q1:
    TwoByOneMux.vhd    : 2X1 MUX using structural modelling
    OnebitFullAdd.vhd  : Sub-component to compute One bit Full Adder made from the ROBDD using only 2x1 muxes
    FourbitFullAdd.vhd : 4-bit Full adder made using the above component
    waveform.zip       : The simulation results

Q2:
    report.pdf         : Contains the Truth table and the Karnaugh map working for minimized expression (for all 3 variables)
    TwoByOneMux.vhd    : 2x1 MUX using structural modelling
    CompL.vhd          : Sub-component to compute 'l' made from the ROBDD using only 2x1 muxes 
    CompG.vhd          : Sub-component to compute 'g' made from the ROBDD using only 2x1 muxes 
    CompE.vhd          : Sub-component to compute 'e' made from the ROBDD using only 2x1 muxes 
    FourbitComp.vhd    : 2-bit comparator made using the above components
    waveform.jpg       : The simulation results

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Assignment 4, Digital Logic Design Lab, Spring 2021, IIT Bombay

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comparatorkarnaugh-mapripple-adderrobdd

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