Pinned Loading

1. ternip ternip Public

   Accelerator for MatmulFree LLM algorithm

   SystemVerilog 14 6

2. sky130_schematics sky130_schematics Public

   Verified visual schematics for all SKY130 Cells

   Tcl 13 17

3. vivado_acorn vivado_acorn Public

   An example repo showing how to get started with the Lite/NiteFury(II) and Sqrl Acorn 101/215(+) FPGAs

   Tcl 9

4. verilog_template verilog_template Public template

   This project demonstrates a scalable format for Verilog including build scripts, design verification, and synthesis.

   Tcl 9 4

5. labs-with-cva6 labs-with-cva6 Public

   Advanced Architecture Labs with CVA6

   SystemVerilog 84 27

6. thesis thesis Public

   Ethan Sifferman Master's Thesis: "Advancing Synthesizable Verilog/SystemVerilog Education with Open-Source Tools and Autograders"

   TeX 4 1