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GeezerVison is showing github.com โ€” suoglu - Overview

@suoglu suoglu Follow
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@suoglu
suoglu
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๐ŸŽฉ
I may be slow to respond.

YiฤŸit SรผoฤŸlu suoglu

๐ŸŽฉ
I may be slow to respond.
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I mostly do stuff with Verilog and some C++ coding, and a little Python and bash scripting.
32 followers ยท 3 following
  • Aachen
  • 15:48 (UTC +01:00)
  • https://suoglu.ylsuo.eu/

Achievements

Achievement: StarstruckAchievement: Arctic Code Vault ContributorAchievement: Pull Shark

Achievements

Achievement: StarstruckAchievement: Arctic Code Vault ContributorAchievement: Pull Shark
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suoglu/README.md
  • ๐Ÿ‘‹ Hi, I am Yigit
  • ๐Ÿ‘€ Iโ€™m interested in RTL design, embedded programming and scripting
  • ๐Ÿ‘พ I mostly use Verilog and C++, sometimes Python and a little bit Bash
  • ๐Ÿ“ซ How to reach me: [email protected] or [email protected]
    • If you have a problem with your homework, please ask it to your instructor
      • I don't really have time to explain stuff to strangers and it is kind a their job
    • If there is an issue with one of the repositories or you want a feature to be added, please use issues
      • I think it is easier to keep track and more transparent
      • Or feel free to implement it yourself; much better as more people contribute!
    • Also open to collaborations in interesting open source projects
  • ๐ŸŒ Also check out suoglu.github.io

Popular repositories Loading

  1. Fixed-Floating-Point-Adder-Multiplier Fixed-Floating-Point-Adder-Multiplier Public

    16-bit Adder Multiplier hardware on Digilent Basys 3

    Verilog 84 14

  2. Pmod Pmod Public

    Collection of simple interfaces for Digilent Pmods

    Verilog 13 5

  3. Digital_Clock Digital_Clock Public

    Verilog code for a digital clock

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  4. HC-SR04 HC-SR04 Public

    Verilog interface for HC-SR04 Ultrasonic Ranging Module

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  5. Verilog-Utilty-Modules Verilog-Utilty-Modules Public

    Collection of utility modules written in Verilog

    Verilog 7 3

  6. Carry-Save-Multiplier Carry-Save-Multiplier Public

    Parameterized and 4-bit carry save multiplier design

    Verilog 6 1

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