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ip-stack

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Here are 11 public repositories matching this topic...

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All 11 VHDL 5 C 4 Python 1 Rust 1
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howerj / ip

Sponsor
Star 5

udp/tcp/ip stack experimentation

c tcp ipv6 udp ipv4 arp ntp ndp ip-stack tcp-stack
  • Updated Jun 25, 2025
  • C

Osbornefrozen840 / esp-smoltcp

Star 4

Run the Rust smoltcp stack as an ESP-IDF component with BSD sockets compatibility for high-performance, memory-safe networking on ESP32 hardware.

rust iot embedded esp32 driver riscv lwip ethernet esp-idf bare-metal no-std emac bsd-sockets ip-stack no-alloc smoltcp esp32-p4 esp-hal esp-component embassy-net
  • Updated Oct 13, 2026
  • C

sjohann81 / ustack

Star 3

A portable and minimalistic IP stack

portable network ipv4 ip network-stack ip-stack
  • Updated Nov 29, 2022
  • C

DatanoiseTV / esp-smoltcp

Sponsor
Star 3

Rust smoltcp IP stack for ESP-IDF — drop-in lwIP-compatible BSD sockets, keeps esp_http_server / esp-tls / esp-mqtt source-compatible. 91 Mbit/s wire-line on ESP32-P4.

rust iot embedded networking tcp esp32 riscv lwip ethernet esp-idf no-std bsd-sockets ip-stack smoltcp esp32-p4 esp-component
  • Updated Jun 14, 2026
  • C

lavrd / tunnel

Star 2

Network tunnel as an example

rust tunnel tun network iptables ip syscalls ioctl tunneling syscall tuntap system-calls network-interfaces unnotifications ip-stack macos-notification-center tun-device macos-notification tun-linux tun-tap
  • Updated Jan 5, 2026
  • Rust

adilsondias-engineer / 06-fpga-udp-parser-mii

Star 0

UDP/IP network stack from scratch (v1) - MII PHY, MAC/IP/UDP parsing in VHDL. First working version with <2μs latency.

fpga udp vhdl xilinx low-latency ethernet mii trading-systems network-stack ip-stack artix-7
  • Updated Jan 24, 2026
  • VHDL

adilsondias-engineer / 06-fpga-udp-packet-parser-rgmii

Star 0

UDP/IP parser for RGMII - Initial implementation (wrong interface for Arty A7). Lesson: Read hardware docs first! See MII versions for correct implementation.

fpga udp vhdl xilinx ethernet ip-stack learning-experience rgmii
  • Updated Jan 24, 2026
  • VHDL

adilsondias-engineer / 06-fpga-udp-parser-mii-v5

Star 0

UDP parser v5 FINAL - Real-time byte-by-byte architecture. 1% → 100% success rate. Production-ready with comprehensive XDC constraints.

real-time fpga udp vhdl xilinx low-latency ethernet production-ready mii trading-systems network-stack ip-stack artix-7
  • Updated Jan 24, 2026
  • VHDL

adilsondias-engineer / 06-fpga-udp-parser-mii-v2

Star 0

UDP parser v2 - Improved MAC filtering and IP checksum validation. Fixed preamble stripping issues.

fpga udp vhdl xilinx low-latency ethernet mii network-stack ip-stack artix-7
  • Updated Jan 24, 2026
  • VHDL

jdimpson / pystack

Star 0

Pure Python Usermode IP Stack

ip-stack usermode-networking
  • Updated Feb 22, 2024
  • Python

adilsondias-engineer / 06-fpga-udp-parser-mii-v3

Star 0

UDP parser v3 - Enhanced with comprehensive debug outputs and performance instrumentation.

debugging fpga udp vhdl instrumentation xilinx ethernet mii ip-stack artix-7
  • Updated Jan 24, 2026
  • VHDL

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