RISC-V Core IP

Syntacore offers a state-of-the-art RISC-V processor IP portfolio, from 32-bit compact MCU cores suitable for deeply embedded applications to high-performance 64-bit 2GHz+ multicore clusters with memory coherency, SMP, and Linux support. All our IPs are configurable, written in SystemVerilog, and are supplied with a complete software development toolkit, an FPGA-based SDK, and comprehensive documentation.

Application-class Cores

Configurable, silicon-proven high-performance Linux-based IPs for applications that demand powerful data processing capabilities. Applicable markets: artificial intelligence, HPC, data centers, AI and ML, and mobile devices.

32/64-bit

SMP up to 4 cores

SCR5

Efficient Linux-capable application core with a 9-stage in-order pipeline, an MMU, L1 and L2 caches, and cache coherency

64-bit

SMP up to 8 cores

SCR7

High-performance Linux-capable application core with a 12-stage dual-issue out-of-order pipeline, and cache coherency

64-bit

SMP up to 16 cores

SCR9

High-performance Linux-capable application core with a 12-stage dual-issue out-of-order pipeline, a VPU, cache coherency, and a hypervisor

Microcontroller-class Cores

Configurable, silicon-proven, area-optimized and energy-efficient RTOS-based cores for deeply embedded applications. Relevant markets: industrial, automotive, internet of things (IoT), sensor fusion, sensors, sensor hubs, control systems, storage, and network devices.

32-bit

SCR1

Open-source compact microcontroller core with a 4-stage in-order pipeline for deeply embedded applications

32/64-bit

SMP up to 4 cores

SCR3

Efficient microcontroller core with a 5-stage in-order pipeline, privilege modes, an MPU, L1 and L2 caches

32/64-bit

SMP up to 4 cores

SCR4

Efficient microcontroller core with a 5-stage in-order pipeline, privilege modes, an FPU, an MPU, L1 and L2 caches

64-bit

SMP up to 4 cores

SCR6

High-performance microcontroller core with a 12-stage dual-issue out-of-order pipeline and a high performance FPU