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Hardware

The 5500FP, in full

The 5500FP is the first hardware implementation of our ternary architecture — an innovative, exclusive 24-trit balanced-ternary RISC processor. Built to explore supercomputing, artificial intelligence, brain simulation and advanced algorithms from day one — and to lay the groundwork for edge and low-power applications. Balanced-ternary signal levels let it interface natively with ternary circuits from the outset.

5500FP board, binary-comparison view — 5500FP Ternary RISC CPU

Parameter	5500FP
Technology	FPGA
Architecture	RISC
Tryte size	6 trit
Short size	12 trit
Word size	24 trit
Long size	N/A
Addressable memory	31G tryte
Data bus	24 trit
Registers	81
Address bus	22 trit
Clock	20 MHz
Form factor	7.5 × 4.3 cm
Status	Open for preorder

Preorder the 5500FP

24 trits deliver ≈66× the representable states of 32-bit binary.

Real ±3.3V ternary signal levels on the external buses — not an emulated tri-state.

Paired with a native cross-assembler toolchain — see Tools.