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GeezerVison is showing github.com β€” Functional Verification Utilities

README.md

FVUtils - Functional Verification Utilities

Modern, Python-centric tools for functional verification engineers and developers

FVUtils is a collection of open-source tools designed to address today's verification challenges. From constrained-random stimulus generation to coverage analysis, transaction tracing to HDL integration, FVUtils provides production-ready solutions for modern verification workflows.

🌐 Visit fvutils.github.io for full documentation, guides, and news!

🎯 Core Projects

PyVSC

Python Verification Stimulus and Coverage - Bring SystemVerilog-style constrained-random and functional coverage to Python
πŸ“š Documentation | πŸ“¦ PyPI

PyHDL-IF

Seamless Python-SystemVerilog integration - Run async pytest tests from SV, call SV functions from Python
πŸ“š Documentation

PyUCIS

Python API for Unified Coverage Interoperability Standard (UCIS) data
πŸ“š Documentation | πŸ“¦ PyPI

PyWellen MCP

LLM-powered waveform analysis via Model Context Protocol - Query VCD/FST/GHW files with natural language
πŸ“š Documentation

DV Transaction Trace

Write transaction-level data from SystemVerilog/Python to beautiful Perfetto traces
πŸ” GitHub

IVPM

Git and Python-centric package manager for managing project dependencies
πŸ“š Documentation

πŸ› οΈ Developer Tools

  • FLTools - EDA filelist parsing and manipulation
  • SVDep - SystemVerilog dependency tracking for incremental builds
  • MKDV - Makefiles for cocotb/pybfm testbenches across multiple simulators
  • vlsim - Python wrapper and run infrastructure for Verilator
  • pytest-fv - Capture HDL test suites via Python unit tests
  • SVT - Simple SystemVerilog testbench library
  • sv-ffi - Medium-level interface between C and SV-DPI

πŸ”¬ Research & Experiments

  • QEMU Model Loader - Technical research on loading QEMU device models as shared libraries
  • VIA - Verification environment introspection API

πŸ“– Visit fvutils.github.io for complete documentation, tutorials, and latest updates

Questions? Open an issue in the relevant project repository or start a discussion!

Popular repositories Loading

  1. pyvsc pyvsc Public

    Python packages providing a library for Verification Stimulus and Coverage

    Python 149 36

  2. pyhdl-if pyhdl-if Public

    Python interface for cross-calling with HDL

    Python 54 13

  3. pyucis pyucis Public

    Python API to Unified Coverage Interoperability Standard (UCIS) Data

    Python 40 17

  4. vte vte Public

    Verification Template Engine is a Jinja2-based template engine targeted at verification engineers

    Python 14 3

  5. py-hpi py-hpi Public archive

    Python/Simulator integration using procedure calls

    Python 10 4

  6. pyucis-viewer pyucis-viewer Public

    QT-based viewer for UCIS coverage data

    Python 9 3

Repositories

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Showing 10 of 48 repositories
  • scvpi Public

    Provides an implementation of (System)Verilog VPI functions for SystemC

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    fvutils/scvpi's past year of commit activity
    C 5 Apache-2.0 2 0 0 Updated Nov 12, 2026
  • dv-solve Public

    Constraint solver focused on the needs of verification

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    fvutils/dv-solve's past year of commit activity
    C 1 Apache-2.0 0 6 0 Updated Nov 10, 2026
  • ivpm Public

    IP and Verification Package Manager

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    fvutils/ivpm's past year of commit activity
    Python 4 BSD-3-Clause 1 0 0 Updated Nov 8, 2026
  • pyucis Public

    Python API to Unified Coverage Interoperability Standard (UCIS) Data

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    fvutils/pyucis's past year of commit activity
    Python 40 Apache-2.0 17 11 5 Updated Nov 5, 2026
  • pyvsc Public

    Python packages providing a library for Verification Stimulus and Coverage

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    fvutils/pyvsc's past year of commit activity
    Python 149 Apache-2.0 36 48 3 Updated Nov 3, 2026
  • pyhdl-if Public

    Python interface for cross-calling with HDL

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    fvutils/pyhdl-if's past year of commit activity
    Python 54 Apache-2.0 13 8 3 Updated Oct 27, 2026
  • sphinx-systemverilog Public

    Sphinx extension for documenting SystemVerilog code

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    fvutils/sphinx-systemverilog's past year of commit activity
    Python 1 Apache-2.0 1 1 3 Updated Oct 24, 2026
  • svcheck Public

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    fvutils/svcheck's past year of commit activity
    C++ 0 Apache-2.0 0 0 0 Updated Oct 21, 2026
  • pyvsc-boolector Public Forked from Boolector/boolector

    Fork of (archived) upstream boolector to provide binary releases for PyVSC

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    fvutils/pyvsc-boolector's past year of commit activity
    SMT 0 72 0 0 Updated Oct 14, 2026
  • ivpm-build Public

    Project build support factored out of ivpm

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    fvutils/ivpm-build's past year of commit activity
    Python 0 Apache-2.0 0 0 0 Updated Oct 4, 2026
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