🖥️ 8 Bit RISC Processor in Verilog 🖥️

An 8-bit RISC based processor designed in verilog with x86 instructions

Directory

./src/* 
  ├─ src/images - # Processor modules and driver simulation results
  ├─ src/ALU.txt - # ALU Module of the processor
  ├─ src/DATAMEM.txt - # 16 Kilo Byte Data Memory
  ├─ src/GROUP00TEST-Driver.txt - # Testing Driver Code for Group 00 Instruction set
  ├─ src/GRP01&11TEST-Driver.txt - # Testing Driver Code for Group 01 && 11 Instruction set
  ├─ src/INSMEM.txt - # Instruction memory with 256 x 24 Bit instruction capability
  ├─ src/PROCESSOR.txt - # Processor module which assembles all sub-modules of the processor
  └─ src/PROCESSOR-STIMULUS.txt - # Processor Driver Code example
./Instruction-Set.pdf - # Driver instructions for the processor
./Doc.pdf - # Architecture and instruction formats

Features

Architecture

Processor

ALU Block

Internal Buses

Control Signals

Instruction Pipeline

Stimulus Results

Arithmetic Instructions

Logical & Misc Instructions

Branch Instructions

Machine Control

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