An abstraction library for interfacing EDA tools

fpga simulation vhdl eda verilog xilinx synthesis vivado altera systemverilog icestorm lattice icarus-verilog modelsim ghdl yosys verilator riviera-pro fossi spyglass

• Updated Sep 15, 2026
• Python

Verilog/SystemVerilog support for VS Code

ctags vscode verilog vivado systemverilog icarus-verilog modelsim hacktoberfest verilog-hdl iverilog bluespec-systemverilog verilator language-server-client systemverilog-support svls

• Updated Nov 11, 2026
• TypeScript

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

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• Updated Nov 25, 2019
• SystemVerilog

Repurposing existing HDL tools to help writing better code

python vim language-server vhdl verilog xilinx syntax-checker systemverilog hdl modelsim questasim ghdl xilinx-vivado lsp-server coc-nvim vim-ale vivado-simulator mentor-msim hdl-checker emacs-lsp

• Updated Sep 23, 2026
• Python

《FPGA应用开发和仿真》（机械工业出版社2018年第1版 ISBN:9787111582786）的源码。Source Code of the book FPGA Application Development and Simulation(CHS).

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• Updated Aug 18, 2026
• Scala

A JSON library implemented in VHDL.

parser json fpga simulation vhdl xilinx synthesis lattice fileformat modelsim questasim ghdl

• Updated Jul 13, 2026
• VHDL

The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB. Read and write transfers on the AHB are converted into equivalent transfers on the APB.

fpga digital verilog modelsim amba apb ahb verilog-project

• Updated Oct 7, 2022
• Verilog

Synthesisable Verilog controller for a 700-space university car park: independent occupancy and availability tracking for university and visitor vehicles against one shared capacity, with a transcript-generating testbench and an Intel Quartus project.

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• Updated Aug 12, 2026
• Verilog

Portable HyperRAM controller

fpga vhdl intel xilinx vivado altera lattice modelsim questasim avalon quartus artix questa hyperram

• Updated Dec 8, 2024
• VHDL

🌊 CLI tool for RTL waveform (VCD/FST/FSDB) inspection

waveform rtl vcs modelsim questasim vcd fst icarus verilator cocotb fsdb xcelium

• Updated Oct 22, 2026
• Rust

合肥工业大学2020年《系统硬件综合设计》（《计算机组成原理》课程设计，CPU）的代码与报告；使用Verilog实现全冒险处理机制的MIPS五段流水CPU，支持MIPS-C3的50条指令。

cpu verilog vivado modelsim mips-c3

• Updated Sep 25, 2020
• Assembly

Исходные коды к главам книги "Цифровой синтез: практический курс" (под ред. А.Ю. Романова и Ю.В. Панчула)

fsm mips tcl labs verilog alu hse modelsim system-verilog mips-architecture quartus-prime quartus miem terasic-de10-lite terasic verilog-designs ddlm schoolmips dmk-press verilog-book

• Updated Sep 15, 2023
• Verilog

Vim plugin to aid VHDL development (for LSP, see https://github.com/suoto/hdl_checker)

productivity vhdl vim-plugins verilog xilinx syntastic syntax-checker altera systemverilog modelsim

• Updated Jun 1, 2021
• Python

The Canny Edge Detection algorithm is implemented on an FPGA using only Verilog code and no Intellectual Property, making it convenient to replicate using any simulator and any of the available FPGA boards, including those from Xilinx and Altera.

fpga vivado modelsim canny

• Updated Apr 22, 2024
• Verilog

Educational VHDL computer with a single-click toolchain for assembly, simulation, and execution on FPGAs

cpu max7219 assembly vhdl isa microworld modelsim ghdl yosys quartus gowin gatemate tang-primer-25k

• Updated Nov 11, 2026
• VHDL

Trying to get a new skill

digital electronics rtl verilog xilinx vivado altera modelsim testbench xilinx-vivado quartus-prime gowin

• Updated Dec 31, 2024
• Verilog

Tutorial de instalação do Quartus Prime no Linux

fpga install-script modelsim quartus-prime quartus-linux fpga-linux

• Updated Oct 16, 2019
• Shell

This repo contains a collection of Verilog+System Verilog+RTL+UVM+Protocols Projects

protocol verification eda rtl verilog systemverilog alu vlsi modelsim uvm verilog-hdl axi apb ahb verilog-project vlsi-design design-verification vlsi-project axi-lite system-verilog-testbench

• Updated May 23, 2026
• SystemVerilog

Single-Cycle RISC-V Processor in systemverylog

verification systemverilog modelsim

• Updated Apr 23, 2019
• SystemVerilog

Custom Altera FPGA designs by Olaoluwa Raji. This repository contains numerous projects that were successfully implemented on an Altera Cyclone IV FPGA using VHDL.

fpga electronics vhdl stm32 embedded-systems modelsim quartus-prime altera-fpga rtl-design-and-verification

• Updated Jun 22, 2026
• VHDL