Source code & scripts for experimental characterization and demonstration of performing NOT and up to 16-input AND, NAND, OR, and NOR operations in real DDR4 DRAM chips. Described in our HPCA'24 paper by Yuksel et al. at https://arxiv.org/abs/2402.18736

dram-characterization processing-in-memory processing-using-dram

• Updated Apr 9, 2024
• VHDL

A flexible memory control framework to reduce the repeated DRAM interface and controller modifications required by DRAM techniques via custom DRAM command extensions and a programmable memory controller, as described in the MICRO 2026 paper by Songara et al.

interface latency parallelism maintenance dram flexibility memory-controller rowhammer processing-using-dram

• Updated Sep 29, 2026
• C++