Opensource DDR3 Controller

fpga controller verilog phy ddr3 memory-controller ddr3-controller ddr3-phy

• Updated Sep 12, 2026
• Verilog

A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs

fpga verilog ddr3 memory-controller

• Updated Dec 1, 2022
• Verilog

mirror of https://git.elphel.com/Elphel/eddr3

fpga zynq ddr verilog xilinx open-core ddr3 memory-controller

• Updated Oct 16, 2017
• Verilog

UEFI memory diagnostic tool - 14 stress tests, per-chip stuck-bit mapping, MCA capture, marathon mode, plain-language verdict with DIMM warranty info

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• Updated May 31, 2026
• C

Opensource DDR4 Controller

linux fpga verilog xilinx phy memory-controller ddr4

• Updated Sep 23, 2026
• Verilog

Multi-Channel DDR Memory Controller Design with BFM-Based Verification and UVM-Style Testbench

system-verilog memory-controller bus-functional-model uvm-verification

• Updated Aug 15, 2026
• Verilog

This is not Linux kernel maintainer's tree, but an open-source work in progress. Officially maintained repositories are under kernel.org (Samsung SoC, memory controller drivers etc.).

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• Updated Nov 12, 2026
• C

The Enhanced SRAM Controller handles secure, efficient memory operations with features like burst mode, error correction, power-saving, and clock domain crossing. It’s perfect for applications requiring robust and reliable memory handling.

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• Updated Oct 21, 2024
• Verilog

A flexible memory control framework to reduce the repeated DRAM interface and controller modifications required by DRAM techniques via custom DRAM command extensions and a programmable memory controller, as described in the MICRO 2026 paper by Songara et al.

interface latency parallelism maintenance dram flexibility memory-controller rowhammer processing-using-dram

• Updated Sep 29, 2026
• C++

A bare-metal SRAM memory controller suitable for Xilinx FPGAs.

fpga verilog sram xilinx memory-controller

• Updated Jan 15, 2024
• Verilog

Xilinx UltraScale+ based HyperBus controller for HyperRam memories

fpga memory xilinx axi-bus memory-controller hyperram hyperbus

• Updated Sep 9, 2026
• C

SystemVerilog and UVM verification of an 8x8 SRAM memory controller with coverage, scoreboard, regression scripts, and bug-demo dashboard.

python tcl verification rtl scoreboard sram regression-testing systemverilog modelsim uvm testbench constrained-random memory-controller questa hardware-verification functional-coverage uvm-verification directed-testing design-verification-project

• Updated May 14, 2026
• SystemVerilog

🛠 A SDRAM controller in Verilog HDL

verilog icarus-verilog verilog-hdl iverilog sdram sdram-controller memory-controller

• Updated Mar 21, 2022
• Verilog

This repository contains a JEDEC-style DDR2 SDRAM controller targeting the memory devices. The controller exposes a simple FIFO-like front-end interface and maps host commands into DDR2 transactions, including full power-up initialization, periodic refresh, scalar and block reads/writes, and DQS-based data capture.

memory rtl verilog digital-design memory-controller ddr2

• Updated Feb 16, 2026
• SystemVerilog

DDR memory controller implementation and verification

ddr verilog systemverilog memory-controller

• Updated Oct 6, 2025

Industrial asynchronous dual-port RAM subsystem in Verilog with CDC synchronizers and AXI-style handshake interface.

fpga verilog xilinx vivado cdc digital-design memory-controller rtl-design dual-port-ram

• Updated Oct 3, 2026
• Verilog

This repository contains a JEDEC-style DDR2 SDRAM controller targeting the memory devices. The controller exposes a simple FIFO-like front-end interface and maps host commands into DDR2 transactions, including full power-up initialization, periodic refresh, scalar and block reads/writes, and DQS-based data capture.

memory rtl verilog digital-design memory-controller ddr2

• Updated Feb 15, 2026
• Verilog

HBM4 System Modeling Platform - High Bandwidth Memory simulation and verification framework

python dram uvm system-verilog hbm semiconductor memory-controller chip-design high-bandwidth-memory hbm4

• Updated Jul 8, 2026
• Python

VHDL controller for the Micron MT55L512Y36F ZBT SRAM: single and burst reads and writes, IOBUF data bus, verified against Micron's model

fpga zynq vhdl sram xilinx vivado testbench digital-design memory-controller zbt-sram

• Updated Oct 28, 2026
• VHDL

Behavioral architecture of a read/write cycle controller for a DRAM chip.

fpga vhdl tcl dram digital-design memory-controller memory-design

• Updated May 26, 2023
• VHDL