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GeezerVison is showing github.com — GitHub - ultraembedded/riscv-linux-boot: Trivial RISC-V Linux binary bootloader

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LICENSE.md
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README.md
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assert.c
assert.c
 
 
assert.h
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boot.S
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csr.h
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custom.ld
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emulation.c
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emulation.h
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exception.c
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exception.h
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main.c
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makefile
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payload.S
payload.S
 
 
sbi.c
sbi.c
 
 
sbi.h
sbi.h
 
 
sbi_interface.h
sbi_interface.h
 
 
serial.c
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serial.h
serial.h
 
 
syscalls.c
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syscalls.h
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Trivial RISC-V Linux Binary Bootloader

Github: http://github.com/ultraembedded/riscv-linux-boot

A very simple bootstrap for starting the Linux kernel on RISC-V.
This takes a vmlinux ELF and a device tree (DTS) file, converts them to binaries, and then embeds these into the bootstrap ELF.

If atomic instruction support is not present on the target platform, the atomic instruction set will be emulated in SW.

This bootloader implements the required SBI calls used by standard RISC-V Linux kernel builds.

Used by the biRISC-V core to boot Linux: http://github.com/ultraembedded/biriscv

Hardware Dependencies

  • UART: Xilinx UARTLite style UART @ 0x92000000
  • Timer: Non-std RISC-V mtime, mtimecmp implementation.

Cloning

git clone https://github.com/ultraembedded/riscv-linux-boot.git

Building

make LINUX_DIR=/path/to/riscv-linux VMLINUX=/path/to/vmlinux[.elf] DTS_FILE=/path/to/config.dts

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Trivial RISC-V Linux binary bootloader

Topics

atomicsbootloaderbootstraplinux-kernelopensbiopensbi-qemu-linuxrisc-vriscv-linuxrv32imuart

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MIT license
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