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GeezerVison is showing riscv.org — Security Register today for RISC-V Summit North America 2027 | San Francisco, California | February 16-18, 2027 RISC-V & SecurityExponential growth in online data and connected devices, including those deployed in critical safety and privacy applications, has increased the potential for consequential security breaches. Security is ranked as a primary concern in diverse segments such as embedded systems, automotive, HPC, and data centers. There is a common need for secure processors that can scale across use-cases and are supported by a broad partner ecosystem that ensures robust implementation and verification Drawing on years of established expertise, the RISC-V ISA has been designed from the bottom up with a security-minded feature set.RISC-V permits the use of optional extensions to enable robust security that scales across a full spectrum of use cases from microcontrollers to HPC. These platforms handle sensitive, high-value data requiring robust confidentiality, integrity, and verifiable execution. They support multi-tenant/multi-level workloads, necessitating scalable isolation mechanisms. This whitepaper outlines how to implement isolation-oriented use cases using RISC-V supervisor domains. It describes both ISA-defined mechanisms (hardware-level) and non-ISA mechanisms (hardware and software) that enable the instantiation and management of isolated supervisor contexts. 
Video: RISC-V Security – Current Initiatives and Future Trends – by Helena Handschuh at RISC-V Summit North AmericaHelena Handschuh, Technical Board Advisor, delivers her Keynote presentation on security at the RISC-V Summit North America.
The RISC-V ISA is flexible and customizable to provide robust scalable security across a wide variety of use cases
Customizable Security FeaturesThe RISC-V ISA is uniquely customizable via extensions allowing a composable approach to security where features and attributes can be added or omitted as applicable to the use case. This permits right-sized security avoiding waste and enabling resource sharing and reuse, where appropriate. 
Scalable Across Use CasesScales across processor use cases, from simple microcontrollers to data centers and HPC. Allows reuse, speeds time to deployment and reduces resource demand for developers of a range of solutions across segments. 
Bespoke SecurityThe extensibility of RISC-V enables users to create bespoke security solutions for niche or special use cases that other architectures do not allow. 
Community Resourced A strong contributory RISC-V ecosystem of security experts enables the pooling of community resources, reducing the individual development resource burden, allowing focus on specific competencies and improving overall performance. RISC-V is secure by design, built with security front of mind to avoid legacy issues and prepared for emerging threats
Secure By DesignThe RISC-V ISA is specifically designed with security first features including multiple privilege levels, PMPs (physical memory protection), secure interprocessing and isolation through TEEs (trusted execution environments) 
Future ProofedAbility to adapt the ISA through extensions to modify security features to future proof against new and emerging threats (e.g, Post Quantum Cryptography). 
Built on Experience As a relatively new ISA, RISC-V draws upon decades of experience to build a secure architecture from the ground up, avoiding known security vulnerabilities and prepared for emerging ones. 
ComprehensiveThe RISC-V ISA comprehensively addresses both the operational security requirements of the application layer and data plus the need to secure specific hardware components. It ensures that assets are protected from unauthorized reading and modification and maintains legitimate access to resources. The RISC-V security ecosystem is evolving and growing to reflect market demand and address requirements
End-to-End EcosystemAs RISC-V adoption gains traction across multiple segments, the ecosystem is expanding to offer end-to-end security solutions that meet market demand and requirements. These include security specific solutions such as implementation and verification tools. 
Heterogeneous and SecureVendors frequently develop SOCs that deploy a heterogeneous mix of processor ISAs. Security ecosystem partners are delivering RISC-V focused solutions that ensure integrity across mixed architectures.
3rd Party InitiativesDevelopers are increasingly actively engaged in 3rd Party industry initiatives to ensure that their RISC-V-based solutions are ahead in addressing newly emerging security approaches (e.g. CHERI). Hear from our Members About RISC-V and SecurityExplore the Latest RISC-V Security Content ChannelLife: Edge AI, security & RISC-V to redefine IoT chips by 2026Channel Life: The IoT semiconductor market is heading into a major shift by 2026, driven by the mainstream adoption of edge AI, the rise of open and modular architectures like RISC-V and chiplets, and increasing…  RISC-V International Staff | Sep 30, 2025 Project Snapshot Post-Quantum Cryptography (PQC) is a topic of increased interest in the past decade, both with regards to the cryptosystem definition and the hardware and software implementations to perform at optimum efficiency. We present…  CVA6 RISC-V PMP Vulnerabilities against FIAProject Snapshot Fault Injection Attacks (FIA) present considerable threats to the security and reliability of embedded systems. FIAs can compromise an embedded processor by altering its clock signal, power supply or by using electromagnetic pulses.…  RISC-V International Staff | Jun 24, 2025 Project Snapshot Post-quantum cryptography (PQC) has garnered significant attention across various communities, particularly with the National Institute of Standards and Technology (NIST) advancing to the fourth round of PQC standardization. One of the leading candidates…  TestRIG – Randomized Testing of RISC-V CPUsTestRIG (Testing with Random Instruction Generation) is a testing framework for RISC-V implementations. The RISC-V community has standardized a formal model of the architecture in the Sail language, giving a human-readable specification that can also…  Akira Tsukamoto, Andrew Moore, Alicia Daleiden, Austin Blackstone, and Daniel Thompson | Aug 22, 2024 Author: Ronan Lashermes, Hardware Security Research Engineer at Inria. Results from a joint work with Hery Andrianatrehina, Joseph Paturel, Simon Rokicki and Thomas Rubiano at Inria. When designing a modern core, achieving peak performance… Subscribe for updates, event info, webinars, and the latest community newsSpecificationRatified
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