CoreFreq : CPU monitoring and tuning software designed for the 64-bit processors.
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Oct 24, 2026 - C
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CoreFreq : CPU monitoring and tuning software designed for the 64-bit processors.
processor tuning process-monitor cpuid arm64 cpu-cache aarch64 cpu-monitoring powerpc ram-info cpu-temperature cpuinfo ryzen ddr3 riscv64 intel-x86-64 ddr4 amd-threadripper amd-epyc dgx-spark
CPU INFOrmation library (x86/x86-64/ARM/ARM64, Linux/Windows/Android/macOS/iOS)
Cycle-accurate pre-silicon simulator of RISC-V and MIPS CPUs
simulator cpu pipeline mips simulation mipt cpu-cache optimizations computer-architecture risc cpu-model risc-v branch-prediction computer-architecture-lesson branch-predictor clock-precise pre-silicon mips-binutils prediction-algorithms
The CacULE CPU scheduler is based on interactivity score mechanism. The interactivity score is inspired by the ULE scheduler (FreeBSD scheduler).
linux freebsd cpu cache scheduler linux-kernel cpu-cache cfs process-scheduler cpu-scheduler ule hrrn cachy-scheduler cachy response-ratio cacule
A survey on architectural simulators focused on CPU caches.
uiomem is a Linux device driver for accessing a memory area outside the Linux Kernel management from user space.
C++ library for storing objects of different types contiguously
CPU cache emulator (LRU)
CPU Cache line invalidation using Golang primitives
Data Oriented Design (DOD) vs. Object Oriented Design (OOD) in action with performance stats.
MIPT-V Pipeline Flowchart Visualizer
simulator cpu pipeline mips simulation mipt cpu-cache optimizations computer-architecture cycle-accurate risc cpu-model prediction-algorithm risc-v branch-prediction computer-architecture-lesson branch-predictor clock-precise pre-silicon
Three same-Big-O experiments (memory access order, branches, boxing) in Java, Python and Node.js, each with a hypothesis written before the run, measured with JMH, pyperf and mitata, and judged on the range across forks.
A lightweight, low-level C++ micro-benchmarking tool designed to accurately measure L1 data cache latency using hardware-aligned pointer chasing to prevent CPU prefetching and speculative execution.
cpp cpp17 low-level cpu-cache system-architecture l1-cache cache-latency pointer-chasing cache-lines
Twelve small benchmarks behind the video "Every Reason Your Code Is Slow, Explained in 14 Minutes": cache order, pointer chasing, false sharing, branches, SIMD, allocation, locks, syscalls.
c benchmark performance optimization simd cpu-cache computer-architecture systems-programming branch-prediction false-sharing
The effect of cache memory on array processing time
C++17 CPU cache locality and matrix multiplication benchmarking, comparing IJK and IKJ loop ordering with correctness tests and performance visualization.
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