GeezerVison

Scraper and adder for Telegram supporting multiple accounts at the same time. Adds via Telegram API and only by username. For adding via ID and not needing Telgram API contact me.

python scraper osint programming telegram script adder

Updated Mar 8, 2023
Python

CallToSta / TG-All-In-One-Tool

Star 164

Scraper, Adder, Forwarder, Copy, Report And More! Easy to use and no coding-knowledge required. A tool to scrape members, add members and many other functions.

telegram adder telegrambot telegramgroups mass-dm members-adding-script telegramscraper scraper-tools members-script telegramadder tele-scraper-bot tele-marketing scraper-telegram shilling-bot telegarm-scrape hidden-members members-adding-scri telegram-scraper2025 telegram-username-checker memberss-scri

Updated Oct 11, 2025
Python

zslwyuan / Basic-SIMD-Processor-Verilog-Tutorial

Star 161

Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first clock cycle will be used to load values into the registers. The second will be for performing the operations. 6-bit opcodes are used to select the fun…

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Updated Jul 17, 2022
Verilog

nxbyte / Verilog-Projects

Star 124

This repository contains source code for past labs and projects involving FPGA and Verilog based designs

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Updated Oct 2, 2019
Verilog

antonblanchard / vlsiffra

Star 123

Create fast and efficient standard cell based adders, multipliers and multiply-adders.

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Updated Sep 20, 2023
Python

Psingh12354 / HackerRank-Certification

Star 102

HackerRank Certification Question

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Updated Jul 18, 2025
Python

suoglu / Fixed-Floating-Point-Adder-Multiplier

Star 84

16-bit Adder Multiplier hardware on Digilent Basys 3

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Updated Aug 3, 2023
Verilog

mongrelgem / Verilog-Adders

Star 78

Implementing Different Adder Structures in Verilog

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Updated Sep 3, 2019
Verilog

evilbream / TG_adder_with_proxy

Star 43

Telegram Group Parser/Scraper and user Adder via id or username with proxy support

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Updated Sep 16, 2024
Python

Essenceia / BFloat16

Star 40

RTL implementation of a performance/area optimized bfloat16 adder and multiplication.

asic verilog floating-point adder multiplier bfloat16 bf16

Updated Mar 28, 2026
Verilog

IamFlea / AdderCircuitGenerator

Star 39

This script generates and analyzes prefix tree adders.

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Updated Apr 9, 2021
Python

sumukhathrey / Verilog_ASIC_Design

Star 35

Verilog for ASIC Design

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Updated Sep 13, 2021
Verilog

RaulMurillo / Flo-Posit

Star 31

Posit Arithmetic Cores generated with FloPoCo

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Updated May 8, 2026
VHDL

Damantha126 / TelegramScraper

Star 19

Using this tool you can easily add so many members from any group to your group. Less than 2 minutes. Super easy. Time saver. But this tool is only for educational purpose. You could be banned from Telegram. So be careful. Recommanded to use this tool only on Termux.

scraper telegram and adder

Updated Jul 11, 2021
Python

2268977258 / 32-bit-FP-Adder-and-Divider

Star 16

32位单精度浮点数加法器和除法器是用于执行符合IEEE 754标准的浮点数加法、除法运算的数字电路。这样的电路设计在现代计算机系统中扮演着重要角色，特别是在处理需要高精度计算的任务时。这个小项目实现了一个符合IEEE 754 单精度浮点数标准（32 位）的浮点数加法器与除法器的完整设计。该设计的目标是通过Verilog分别实现能够处理两输入浮点数的加法和除法运算模块。

linux verilog vcs floating-point adder divider