A CPU implemented in a modular synthesizer

modular synthesizer cpu-emulator processor-design

• Updated Mar 20, 2022

HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V processor using SystemVerilog and FPGA tools. Developed by TU Graz's EAS Group, this resource combines hands-on exercises in hardware/software co-design with practical implementation on the Basys3 FPGA board.

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• Updated Feb 2, 2026
• SystemVerilog

Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first clock cycle will be used to load values into the registers. The second will be for performing the operations. 6-bit opcodes are used to select the fun…

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• Updated Jul 17, 2022
• Verilog

CPU Design Based on RISCV ISA

integrated-circuits processor-design

• Updated Jun 14, 2024
• Verilog

🎓 Instructional RISC-V processor design framework: single-cycle to 5-stage pipeline with FPGA verification and complete learning guidelines! A RISC-V CPU design guideline.

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• Updated Feb 2, 2026
• Verilog

tinyGPU: A Predicated-SIMD processor implementation in SystemVerilog

gpu simd systemverilog hdl computer-organization processor-design

• Updated Jul 14, 2021
• SystemVerilog

Chisel implementation of Neural Processing Unit for System on the Chip

chisel3 system-on-chip processor-design npu

• Updated Nov 4, 2026
• Scala

Design and documentation for a very simple 4-bit processor named NibbleBuddy and its assembler.

assembly assembler verilog computer-architecture instruction-set-architecture computer-organization hardware-description-language processor-design single-cycle-processor

• Updated Dec 7, 2024
• Verilog

A multi-cycle RISC CPU (processor) like MIPS-CPU architecture in VHDL ( a hardware-side implementation )

processor-architecture cpu vhdl isa cpu-model instruction-set-architecture mips-processor vhdl-modules risc-processor vhdl-code cpu-architecture multi-cycle processor-design

• Updated Jun 19, 2021
• VHDL

CSC403: Computer Organization and Architecture [COA] & CSL403: Processor Architecture Lab [PAL] | SE Semester IV | Computer Engineering

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• Updated Sep 5, 2026
• HTML

u[Dark]RISC -- "micro-darkrisc" -- an early 16-bit micro-RISC processor defined before DarkRISCV

cpu fpga core processor rtl verilog risc softcore processor-design

• Updated Jul 25, 2023
• Verilog

Single-Cycle RISC-V Processor using SystemVerilog on a Nexys A7 (Artix-7) FPGA. Project includes complete datapath and control logic with instruction memory, data memory, ALU, immediate generator, and branch comparator. It supports the complete RV32I instruction set (R, I, S, B, U, J types).

fpga vivado computer-architecture system-verilog risc-v cpu-architecture processor-design single-cycle-processor digital-design-and-computer-organization rv32i-processor

• Updated Nov 10, 2026
• SystemVerilog

EE577b-Course-Project

verilog-hdl multiprocessor processor-design networkonchip synopsys-dc cadence-ncverilog cadence-conformal

• Updated May 6, 2020
• Verilog

Codex skills for Chisel/RISC-V processor development: microarchitecture, RTL verification, Vivado timing analysis, and FPGA optimization.

fpga chisel rtl chisel3 vivado risc-v processor-design cpu-designs loongarch agent-skills codex-cli codex-skills

• Updated Oct 23, 2026
• Python

Design and verification of a simple pipelined RISC processor in Verilog, featuring a five-stage pipeline and custom ISA.

verilog pipelining computer-architecture risc processor-design

• Updated Jul 15, 2024
• Verilog

8-bit RISC Processor on Logisim

circuit-simulator logisim processor-design

• Updated Oct 1, 2020

SARV A Risc-V

processor-architecture cpu pipeline core processor verilog computer-architecture risc-v processor-design sarv digital-design-and-computer-architecture

• Updated Nov 4, 2026
• Verilog

A fully pipelined 5-stage RV32I processor implemented in SystemVerilog. This design models instruction-level parallelism with forwarding and hazard detection, and passes all RISCOF compliance tests for the RV32I base ISA.

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• Updated Jul 27, 2025
• SystemVerilog

The Voyager flight computer on SKY130 silicon. 58 cells. Currently 24 billion km away.

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• Updated Aug 11, 2026
• Verilog

NanoGo a Go (golang) Subset for Homebrew / Hobby CPUs

go golang cpu compiler assembly hobby-project hobby-compiler processor-design hobby-language homebrew-computer

• Updated Nov 8, 2025
• Go