Chisel: A Modern Hardware Design Language

scala chip-generator chisel rtl chisel3 firrtl verilog

• Updated Nov 11, 2026
• Scala

MyLayout is a powerful iOS UI framework implemented by Objective-C. It integrates the functions with Android Layout,iOS AutoLayout,SizeClass, HTML CSS float and flexbox and bootstrap. So you can use LinearLayout,RelativeLayout,FrameLayout,TableLayout,FlowLayout,FloatLayout,PathLayout,GridLayout,LayoutSizeClass to build your App 自动布局 UIView UITab…

android ios ui uitableview uicollectionview xcode view css3 layout cocoapods xib storyboard constraints rtl grid-layout autolayout uiscrollview flexbox-layout layoutsubviews sizeclasses

• Updated Mar 15, 2026
• Objective-C

Verilator open-source SystemVerilog simulator and lint system

cpp rtl verilog compilers systemc system-verilog verilator verilog-simulator

• Updated Nov 12, 2026
• SystemVerilog

Rocket Chip Generator

scala rocket-chip chip-generator chisel riscv rtl

• Updated Sep 13, 2026
• Scala

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

cpp tcl eda rtl verilog def gdsii timing-analysis openroad lef opendb-database

• Updated Nov 12, 2026
• Verilog

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

boom rocket rocket-chip chip-generator chisel riscv rtl peripherals soc out-of-order superscalar risc-v firesim accelerators chipyard hwacha

• Updated Nov 10, 2026
• Scala

Fast Swift Views layouting without auto layout. No magic, pure code, full control and blazing fast. Concise syntax, intuitive, readable & chainable. [iOS/macOS/tvOS/CALayer]

swift language swift-library ios cocoapod layout carthage layout-engine rtl swift-framework swift-3 ios-swift anchor ios-ui ios-lib margin chainable-methods uiview-extension left-language

• Updated Jul 23, 2025
• Swift

SonicBOOM: The Berkeley Out-of-Order Machine

scala berkeley boom rocket-chip chisel riscv rtl riscv-boom

• Updated Nov 2, 2026
• Scala

Scala based HDL

scala fpga vhdl rtl verilog

• Updated Oct 30, 2026
• Scala

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

magic asic rtl verilog vlsi foundry yosys klayout caravel netgen system-on-chip openroad openram skywater 130nm soc-design rtl2gds

• Updated Mar 25, 2026
• Python

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

asic fpga hardware rtl ip systemverilog axi network-on-chip axi4 axi4-lite

• Updated Nov 11, 2026
• SystemVerilog

Framework for transforming Cascading Style Sheets (CSS) from Left-To-Right (LTR) to Right-To-Left (RTL)

css i18n postcss css3 mirror ltr rtl cascading-style-sheets postcss-plugin flip rtlcss right-to-left left-to-right

• Updated Feb 18, 2025
• JavaScript

Modular hardware build system

asic fpga hls vhdl eda rtl verilog make synthesis cmos

• Updated Nov 12, 2026
• Python

Veryl: A Modern Hardware Description Language

rust rtl verilog systemverilog hdl

• Updated Nov 12, 2026
• Rust

A simple yet powerful JQuery star rating plugin with fractional rating support.

javascript css jquery rating css-styles rtl caption star bootstrap-star-rating rate-control change-stars star-symbols fractional

• Updated Mar 22, 2023
• JavaScript

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

core riscv rtl ip verilog risc-v rv32i rv32e rv32imc rv32emc

• Updated Nov 15, 2024
• SystemVerilog

VeeR EH1 core

fpga processor riscv rtl risc risc-v open-source-hardware fusesoc verilator riscv32 western-digital axi4 ahb-lite asic-design veer

• Updated Jul 16, 2026
• SystemVerilog

Various HDL (Verilog) IP Cores

audio asic fpga usb rtl verilog spi sram uart verilog-hdl verilog-components verilator i2s sdram

• Updated Jul 1, 2021
• Verilog

An FPGA-based USB 1.1 (full-speed) device core to implement USB-serial, USB-camera, USB-audio, USB-hid, etc. It requires only 3 FPGA common IOs rather than additional chips. 基于FPGA的USB 1.1 (full-speed) device端控制器，可实现USB串口、USB摄像头、USB音频、U盘、USB键盘等设备，只需要3个FPGA普通IO，而不需要额外的接口芯片。

keyboard fpga usb rtl verilog cdc uvc usb-controller usb-hid usb-audio usb-uart usb-cdc usb-serial usb-keyboard usb-device usb-camera usb-microphone usb-uvc usb-speaker usb-disk

• Updated Dec 6, 2024
• Verilog

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware

linux fpga zynq hls hardware vhdl rtl verilog xilinx sdr wi-fi analog-devices ieee80211 dma software-defined-radio ofdm csma ad9361 mac80211

• Updated Oct 13, 2026
• Verilog