AMBA AXI VIP

vip systemverilog uvm axi amba axi4 amba-axi

• Updated Oct 1, 2026
• SystemVerilog

Code generation tool for control and status registers

asic fpga vhdl eda rtl verilog csr systemverilog soc uvm ral axi amba apb systemrdl register-descriptions wishbone-bus uvm-ral-model uvm-register-model wiki-documents

• Updated Sep 11, 2026
• Ruby

Parametric AXI4 crossbar in SystemVerilog

arm asic fpga processor riscv verilog soc fpga-soc interconnect amba crossbar riscv32 axi4 axi4-lite riscv64 monodraw axi4-protocol asic-design axi4-full

• Updated May 25, 2026
• SystemVerilog

Control and status register code generator toolchain

asic fpga eda verilog csr command-line-tool systemverilog uvm registers axi amba apb register-descriptions systemrdl-compiler hardware-description-language uvm-register-model

• Updated Oct 26, 2026
• Python

Network on Chip Implementation written in SytemVerilog

systemverilog uvm noc axi amba network-on-chip axi4 amba-axi

• Updated Aug 27, 2022
• SystemVerilog

Education kit for teaching introductory Arm-based system-on-chip design on FPGA with lectures and practical labs (educational)

arm fpga cortex-m vhdl cmsis hardware-designs soc teaching-materials arm-cortex-m0 system-on-chip amba ahb soc-design keil-mdk system-on-chip-design design-start education-kit

• Updated Oct 7, 2025
• HTML

Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.

arm verilog axi amba apb ahb

• Updated May 14, 2021
• Verilog

Education kit for teaching advanced Arm Cortex-A system-on-chip design on FPGA platforms with lectures and hands-on labs (educational)

arm fpga vhdl embedded-systems armv7 vivado hardware-designs teaching-materials cortex-a zybo amba cortex-a9 arm-cortex-a9 soc-design system-on-chip-design zybo-z7-10 education-kit

• Updated Oct 7, 2025
• HTML

Education kit for teaching efficient embedded systems design on Arm Cortex-M platforms with labs and lecture materials (educational)

arm embedded cortex-m embedded-systems computer-engineering hardware-designs armv8 teaching-materials trustzone amba nucleo arm-cortex-m4 keil-mdk embedded-system-design st-nucleo-f401re arm-cortex-m33 discovery-f4 st-nucleo-l552ze education-kit

• Updated Oct 7, 2025
• C

AHB3-Lite Interconnect

switch interconnect amba ahb3-lite

• Updated May 10, 2024
• SystemVerilog

The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB. Read and write transfers on the AHB are converted into equivalent transfers on the APB.

fpga digital verilog modelsim amba apb ahb verilog-project

• Updated Oct 7, 2022
• Verilog

Textbook on system-on-chip design using Arm Cortex-M microcontrollers covering AMBA, peripherals, and embedded software (educational)

arm fpga embedded-systems textbook cmsis soc fpga-soc trustzone amba

• Updated Jun 16, 2025

Parameterised Asynchronous AHB3-Lite to APB4 Bridge.

amba apb ahb3-lite apb-bridge

• Updated May 10, 2024
• SystemVerilog

Reference book for SoC and FPGA designers integrating Arm Cortex-M processors with AMBA bus architectures (educational)

arm fpga cortex-m embedded-systems software-design amba arm-cortex-m hardware-design soc-design keil-mdk system-on-chip-design bus-architecture cortex-m-processors reference-book

• Updated Jun 16, 2025

数字IC验证学习笔记：SV/UVM/AMBA总线（AXI/APB/AHB/AXI-Lite/AXI-Stream）+ 数字IC验证校招面经

verification verilog systemverilog uvm axi amba

• Updated Oct 17, 2026

Open-source AMBA CHI infrastructures (supporting Issue B, E.b)

testing cpp chi amba software-modeling chi-b chi-eb amba-chi

• Updated Nov 10, 2026
• C++

Assertion-Based Formal Verification of an AHB2APB bridge, featuring SystemVerilog assertions, RTL designs, and detailed documentation including a final report and project progression presentation.

verification abp uvm formal-verification amba ahb harward computer-ar assertion-based-verification ahb2

• Updated Mar 23, 2024
• SystemVerilog

Verification IP for AMBA APB Protocol

vip systemverilog uvm amba apb

• Updated Nov 7, 2023
• SystemVerilog

Master and Slave made using AMBA AXI4 Lite protocol.

design verilog amba axi4-lite

• Updated Oct 9, 2020
• Stata

APB master and slave developed in RTL.

rtl verilog systemverilog amba apb

• Updated Oct 25, 2025
• SystemVerilog