Rocket Chip Generator

scala rocket-chip chip-generator chisel riscv rtl

• Updated Sep 13, 2026
• Scala

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

boom rocket rocket-chip chip-generator chisel riscv rtl peripherals soc out-of-order superscalar risc-v firesim accelerators chipyard hwacha

• Updated Nov 10, 2026
• Scala

SonicBOOM: The Berkeley Out-of-Order Machine

scala berkeley boom rocket-chip chisel riscv rtl riscv-boom

• Updated Nov 2, 2026
• Scala

FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility

cloud fpga hardware simulation boom rocket-chip risc-v datacenter on-prem firesim

• Updated Nov 3, 2026
• Scala

Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel

neural-network hardware rocket-chip chisel riscv rtl rocc

• Updated Jan 23, 2020
• Scala

RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards

zynq linux-kernel rocket-chip gsoc gsoc-2016 zedboard petalinux parallella risc-v rocket-core

• Updated Nov 14, 2018
• SystemVerilog

Tests for example Rocket Custom Coprocessors

rocket-chip riscv rocc

• Updated Feb 19, 2020
• C

The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freely available components.

fpga rocket-chip riscv verilog soc risc-v oshw osh chipyard

• Updated Dec 1, 2022
• C

Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)

rocket-chip vivado risc-v linux-boot fpga-board zcu102 zynqmp

• Updated Mar 21, 2023
• Tcl

Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator used in FireSim.

rocket-chip soc risc-v

• Updated Nov 24, 2019
• C

A fault-injection framework using Chisel and FIRRTL

rocket-chip chisel firrtl fault-injection risc-v rocc

• Updated Sep 17, 2025
• Scala

This repository contains the hardware design source files of the Hex Five X300 RISC-V SoC. The X300 is Hex Five's official reference HW platform for its MultiZone Trusted Execution Environment and MultiZone Trusted Firmware. The X300 is an enhanced secure version of the SiFive's Freedom E300 built around the Rocket chip developed at U.C. Berkeley.

fpga rocket-chip xilinx fpga-soc risc-v xilinx-fpga bitstream digilent e300 sifive artix-100t sifive-freedom arty-a7 artix-35t

• Updated Jan 23, 2024
• Scala

Run Rocket Chip on VCU128

rocket-chip risc-v vcu128

• Updated Oct 21, 2025
• Tcl

A template for building new projects/platforms using the BOOM core.

scala boom rocket-chip chisel riscv rtl

• Updated Jan 14, 2019
• Shell

Network components (NIC, Switch) for FireBox

network rocket-chip chisel nic risc-v

• Updated Oct 27, 2024
• Scala

BOOM's Simulation Accelerator.

simulation accelerator boom rocket rocket-chip chisel riscv rtl firrtl soc risc-v verilator chipyard

• Updated Dec 16, 2021
• Scala

A simple baremetal program template for RISC-V inspired from riscv benchmark tests

rocket-chip risc-v riscv-sim

• Updated Apr 17, 2018
• C

scala rocket-chip chisel vpu rvv

• Updated Jan 9, 2021
• Scala

Parallella RISC-V Prebuilt Images

zynq linux-kernel rocket-chip gsoc gsoc-2016 zedboard parallella risc-v board-parallella

• Updated Aug 18, 2016

😱 RoCC Accelerator Integration with Chipyard

scala sbt integration hardware simulation rocket rocket-chip chisel chisel3 computer-architecture hardware-acceleration risc-v verilator rocc accelerators chipyard

• Updated Nov 6, 2024