The PoC Library has been forked to github.com/VHDL/PoC. See new address below

python asic fpga simulation vhdl verification xilinx synthesis regression-testing altera hardware-designs lattice hardware-libraries poc-library vlsi testbenches hardware-modules osvvm uvvm vunit

• Updated Jul 30, 2025
• VHDL

A flexible and scalable development platform for modern FPGA projects.

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• Updated Nov 2, 2026
• Python

Scripts to build and use docker images including GHDL

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• Updated Nov 20, 2024
• Shell

Tests to evaluate the support of VHDL 2008 and VHDL 2019 features

fpga simulation vhdl vunit cosimulation

• Updated Jan 30, 2025
• VHDL

Interfacing VHDL and foreign languages with VUnit

python unit-testing vhdl ffi verification dpi vunit vpi cosimulation vhpidirect

• Updated Feb 20, 2020
• Python

This repository contains VHDL implementations for all hardware design challenges (quests/questions) featured on the chipdev.io website.

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• Updated Oct 7, 2026
• VHDL

Co-simulation and behavioural verification with VHDL, C/C++ and Python/m

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• Updated Nov 12, 2026
• VHDL

A simple Emacs minor mode for VUnit

package emacs vhdl vunit

• Updated Jul 14, 2025
• Emacs Lisp

Containerized open and free development tools for Dynamic Binary Hardware Injection (DBHI)

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• Updated Jan 24, 2023
• Dockerfile

Parameterised VHDL templates for Neovim — entities, FSMs, CDC, AXI4-Lite and testbenches, rendered from Lua rather than pasted.

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• Updated Sep 25, 2026
• VHDL

VUnit-by-HGB is a VS-Code extension which enables the testexplorer for VUnit projects.

vhdl vscode-extension vunit unittesting digital-design regressiontesting

• Updated Jun 9, 2026
• TypeScript

Reusable HDL modules, packages, and testbench utilities for FPGA and ASIC development, supporting both VHDL and Verilog.

simulation vhdl rtl hdl testbenches osvvm vunit vhdl-modules vhdl-code vhdl2008 vhdl-testbench vhdl-2008 eda-playground

• Updated Oct 24, 2026
• VHDL

A VHDL code base that contains Utility Packages for both HDL and Testbenches

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• Updated Aug 19, 2025
• VHDL

[TFM] This repo contains the work developed in the SIEAV Master practices 🎓✏️📚

fpga master-thesis ghdl vunit neorv32 sieav

• Updated Jan 23, 2025
• VHDL

Modern bazel rules to describe and simulate vhdl.

vhdl bazel-rules ghdl vunit cocotb nvc

• Updated Oct 26, 2026
• Starlark

FPGA verification demo using VHDL, VUnit, and SymbiYosys with GitHub Actions CI integration.

fpga vhdl ghdl formal-verification vunit github-actions-ci symbiyosys

• Updated Jan 19, 2026
• VHDL

Reusable FPGA signal-chain IP (ADC → DSP → DAC) on Zynq/ZedBoard: AXI4-Stream cores, UVVM/VUnit-verified, CI-tested.

fpga zynq signal-processing dsp vhdl xilinx vivado ghdl uvvm vunit zedboard pmod hardware-verification axi4 axi4-stream

• Updated Nov 10, 2026
• VHDL

Write unit tests against your Vue components using mocha and @vue/test-utils

unit-testing mocha vue-components code-coverage vunit

• Updated Jan 7, 2023
• JavaScript

SublimeText3 bits for Quartus, ModelSim, and VUnit Integration mirror of https://phabricator.kairohm.dev/diffusion/10/

sublime-text systemverilog modelsim vunit quartus

• Updated Sep 9, 2018
• SystemVerilog

VHDL-2008 DCF77 receiver/decoder (AM + PM) with AXI4-Lite interface, VUnit/GHDL testbenches

fpga vhdl sdr ghdl vunit dcf77 time-signal

• Updated Nov 8, 2026
• VHDL