OpenCL is the most powerful programming language ever created. Yet the OpenCL C++ bindings are cumbersome and the code overhead prevents many people from getting started. I created this lightweight OpenCL-Wrapper to greatly simplify OpenCL software development with C++ while keeping functionality and performance.

amd gpu opencl intel nvidia gpgpu gpu-acceleration gpu-computing vectorization rocm gpu-programming gpgpu-computing amd-gpu vector-processor geforce intel-arc

• Updated Nov 9, 2026
• C++

RISC-V Zve32x Vector Coprocessor

systemverilog coprocessor risc-v vector-processor

• Updated Jan 22, 2026
• Assembly

Vector processor for RISC-V vector ISA

riscv systemverilog risc-v vector-processor

• Updated Oct 19, 2020
• SystemVerilog

Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra

vector-processor risc-v64 reproducible-computation

• Updated Dec 19, 2021
• Verilog

An Extended Version of the T0x multithreaded cores, with a custom general purpose parametrized SIMD/MIMD vector coprocessor and support for 3-5 way superscalar execution. The core is pin-to-pin compatible with the RISCY cores from PULP

accelerator simd riscv superscalar klessydra t02x t03x pulpino t13x vector-processor mimd

• Updated Aug 24, 2024
• VHDL

Development and simulation framework for Application Specific Vector Processor

data-driven dsp architecture simd simulation-framework digital-signal-processing cycle-accurate systemc model-based network-on-chip heterogeneous-computing vector-processor single-instruction-multiple-data asip application-specific system-simulation vector-core heterogeneous-structure system-level-simulation multimode-processing

• Updated Mar 8, 2020
• C++

Design of Banked Memory Access Unit for Load Store Instructions of a 32-bit Vector Processor

memory verilog cpu-design vector-processor

• Updated Nov 29, 2018
• Verilog

Implementation of Vector Reduce Min and Vector Negation ASIC Hardware, plus a toy CPU, memory and custom ISA for demo. Can be compiled to Verilog. Demos include fib series computations using custom ISA (and custom assembly) and some vector programs.

processor-architecture ram hardware processor bus bluespec hardware-designs vlsi hardware-acceleration vlsi-physical-design bluespec-systemverilog processor-design vector-processor vlsi-design bluespec-systemverilog-language vlsi-cad

• Updated Jan 11, 2021
• Bluespec

A RISC-V vector processor written in Chisel HDL.

fpga processor chisel risc-v vector-processor

• Updated Jul 10, 2022
• Scala

Vector ASIP for the application of filters to an image 🖼️

fpga vhdl computer-architecture vector-processor pipelined-processors

• Updated May 19, 2022
• SystemVerilog

128-bit SIMD vector coprocessor extension (HVX) for PicoRV32 — 16×int8/8×int16/4×int32 saturating lanes, 64-bit MAC accumulator, PCPI attachment

mac embedded fpga dsp simd systemverilog risc-v picorv32 rv32 vector-processor custom-instructions

• Updated Jul 25, 2026
• SystemVerilog

functional and timing simulator for VMIPS-like vector architecture

computer-architecture timing-simulator vector-processor functional-simulator

• Updated May 3, 2026
• Python

A small vector core, its reference simulator, and a compiler that lowers quantized neural networks onto its 16 instructions.

simulator compilers code-generation register-allocation quantization vector-processor

• Updated Jul 28, 2026
• Python

Hand-written SystemVerilog SIMD core (Fall 2025) followed by an Allo DSL/HLS redesign adding INT8 GEMM, ReLU, and fusion kernels (Spring 2026), targeting the Nexys A7.

fpga hls systemverilog vector-processor hardware-accelerator vitis-hls

• Updated May 1, 2026
• Python

Un simulador moderno para aprender arquitectura de computadores. Tiene editor con resaltado de sintaxis, cronograma interactivo del pipeline, registros y memoria en tiempo real, y soporte para instrucciones enteras, de punto flotante y vectoriales.

typescript pipeline assembly monaco-editor computer-architecture hazard-detection dlx processor-simulator tomasulo branch-prediction superescalar cpu-simulator instruction-level-parallelism vector-processor arquitectura-de-computadores out-of-order-execution reorder-buffer angular21

• Updated Oct 24, 2026
• TypeScript

Ara on ZCU102 over Cheshire SoC

fpga ara pulp cheshire zcu102 vector-processor

• Updated Nov 4, 2026
• Assembly

ОТКРЫТЫЙ КОНЦЕПТ x128/x512 Микроэлектроника зашла в тупик нанометров . Концепт решает проблему расширением регистров и сокращением тактов. Вместо 4–8 шагов x64, логика x128/x512 обрабатывает массивы (ИИ, криптография) за 1–2 такта. Реализация: чиплеты через UCIe и софтверный JIT для совместимости с x86. Безвозмездно передаю идею человечеству.

open-source-hardware vector-processor chiplet ucie

• Updated Jul 10, 2026