A graphical processor simulator and assembly editor for the RISC-V ISA
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Nov 11, 2026 - C++
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Intel® Performance Counter Monitor (Intel® PCM)
windows linux freebsd processor-architecture energy cpu monitoring osx processor intel performance-metrics power xeon performance-visualization performance-dashboard pcm performance-analysis monitor-performance performance-monitoring performance-counters
GPGPU microprocessor architecture
💻 An assembler for custom, user-defined instruction sets! https://hlorenzi.github.io/customasm/web/
rust processor-architecture vm bytecode compiler custom virtual-machine assembly asm assembler webassembly rust-lang customizable assembly-language microprocessor instruction-set-architecture machine-code bytecode-compiler instruction-set user-defined
RISC-V Guide. Learn all about the RISC-V computer architecture along with the Development Tools and Operating Systems to develop on RISC-V hardware.
processor-architecture simulator processor virtualization hypervisor optimize platformio riscv peripherals android-app computer-architecture cpu-profiling sbc risc-v sel4 risc-processor rv32 riscv64 tensoflow-lite riscv-emulator
Lightweight recording and sampling of performance counters for specific code segments directly from your C++ application.
linux processor-architecture library performance cpp perf performance-metrics cpp17 performance-analysis sampling performance-monitoring system-programming performance-counters performance-measurement performance-analyses instruction-based-sampling processor-event-based-sampling
HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V processor using SystemVerilog and FPGA tools. Developed by TU Graz's EAS Group, this resource combines hands-on exercises in hardware/software co-design with practical implementation on the Basys3 FPGA board.
processor-architecture pipelines riscv vivado systemverilog computer-architecture gtkwave system-verilog university-course risc-v c-programming rv32i open-education verilator open-educational-resources processor-design assembly-programming hardware-software-codesign microcontroller-design
WebRISC-V: A Web-Based Education-Oriented RISC-V Pipeline Simulation Environment [PHP]
php education processor-architecture simulator pipeline assembly computer-architecture risc risc-v pipeline-simulation-environment
SST Architectural Simulation Components and Libraries
processor-architecture simulator networking simulation hpc memory cache processor trace network-analysis cache-simulator system-design snl-other snl-performance-workflow
Sunflower Full-System Hardware Emulator and Physical System Simulator for Sensor-Driven Systems. Built-in architecture modeling of Hitachi SH (j-core), RISC-V, and more.
processor-architecture simulator embedded-systems j-core riscv cross-compiler network-simulator emulators processor-simulator superh hitachi riscv32 battery-simulator power-simulator riscv-sim riscv-simulator riscv-emulator
A multi-cycle RISC CPU (processor) like MIPS-CPU architecture in VHDL ( a hardware-side implementation )
processor-architecture cpu vhdl isa cpu-model instruction-set-architecture mips-processor vhdl-modules risc-processor vhdl-code cpu-architecture multi-cycle processor-design
A minimalistic single-cycle RISC-V platform for demonstrational and educational purposes in Logisim Evolution.
CSC403: Computer Organization and Architecture [COA] & CSL403: Processor Architecture Lab [PAL] | SE Semester IV | Computer Engineering
computer-science processor-architecture engineering computer-engineering computer-architecture textbooks logisim microprogramming computer-organization booths-algorithm processor-design university-of-mumbai cache-mapping ameythakur amey megasatish reference-books ameyarc amey-thakur processor-architecture-lab
Super scalar Processor design
processor-architecture bison flex processor assembler parallel-computing verilog forwarding bypassing pipeline-processor superscalar opcode verilog-hdl instruction-set-architecture instruction-set processor-simulator branch-prediction pipeline-cpu mnemonics instruction-level-parallelism
A collection of my cources, lectures, articles and presentations
computer-science processor-architecture lectures cpu presentations computer-engineering computer-architecture digital-design
Senior Design Project at UW-Madison ECE
A simulation of the Tomasulo algorithm, a hardware algorithm for out-of-order scheduling and execution of computer instructions, written in C++.
Collected article documents in PDF covering subject with co-simulation, embedded systems, software development and logic design and verification
processor-architecture documentation usb dsp eda embedded-systems freertos ethernet osvvm risc-v instruction-set-simulator pcie logic-design embedded-software co-simulation system-modelling logic-simulation memory-subsystem system-on-chip-design vproc
SARV A Risc-V
processor-architecture cpu pipeline core processor verilog computer-architecture risc-v processor-design sarv digital-design-and-computer-architecture
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