GV

GeezerVison

The World Wide Web, restored to 800 pixels of glory.

Home|About|Gaming cabinet|Archives|How it works|Starter sites

On this site

  • Home
  • Systems & Design
  • Low Power - High Performance
  • Manufacturing, Packaging & Materials
  • Test, Measurement & Analytics
  • Auto, Security and AI
  • Special Reports
  • Business & Startups
  • Jobs
  • Knowledge Center
  • Technical Papers
  • AI/ML/DL
  • Architectures
  • Automotive/ Aerospace

This view

  • Original page
  • New address

GeezerVison is showing semiengineering.com — ARM Archives

Subscribe
  • Home
  • Systems & Design
  • Low Power - High Performance
  • Manufacturing, Packaging & Materials
  • Test, Measurement & Analytics
  • Auto, Security and AI
  • Special Reports
  • Business & Startups
  • Jobs
  • Knowledge Center
  • Technical Papers
    • Home
    • ';
    • AI/ML/DL
    • Architectures
    • Automotive/ Aerospace
    • Communication/Data Movement
    • Design & Verification
    • Lithography
    • Manufacturing
    • Materials
    • Memory
    • Optoelectronics / Photonics
    • Packaging
    • Power & Performance
    • Quantum
    • Security
    • Test, Measurement, Analytics tech papers
    • Transistors
    • Z-End Applications
  • Events & Webinars
    • Events
    • Webinars
  • Videos & Research
    • Videos
    • Industry Research
  • Newsletters & Store
    • Newsletters
    • Store
  • MENU
    • Home
    • Special Reports
    • Systems & Design
    • Low Power-High Performance
    • Manufacturing, Packaging & Materials
    • Test, Measurement & Analytics
    • Auto, Security and AI
    • Knowledge Center
    • Videos
    • Startup Corner
    • Business & Startups
    • Jobs
    • Technical Papers
    • Events
    • Webinars
    • Industry Research
    • Newsletters
    • Store
    • Special Reports
Home > Low Power-High Performance > Introduction To FP8 Formats: Part 1

tag: ARM

Introduction To FP8 Formats: Part 1

By Siyu Mou - 12 Nov, 2026 - Comments: 0

The industry is moving from high-precision formats (FP32, FP16, BF16) to lower-precision data types for Machine Learning (ML) inference and training. In cloud and data center environments, lower-precision data types deliver higher throughput by packing more compute per cycle from the same platform. On edge and mobile devices, smaller formats reduce model size, memory footprint and bandwidth, wh... » read more

Blog Review: Nov. 11

By Jesse Allen - 11 Nov, 2026 - Comments: 0

Synopsys' Charlie Matar finds that interconnects are becoming more influential components of both the silicon and system architecture, with AI infrastructure compute scaling only if data reaches the right processor at the right time at an acceptable power cost. Siemens' Bhanu Pandey warns that floating nets in analog power-down circuits represent a hidden reliability risk that can evade even... » read more

Chip Industry Week In Review

By The SE Staff - 06 Nov, 2026 - Comments: 0

Top Of The Week Nvidia's board of directors issued a statement that it was investigating CEO Jensen Huang, following his admission that he had an intimate relationship with a purported Chinese spy. The affair surfaced as part of investigation by the U.S. government into illegal shipments of Nvidia AI chips to China, according to the New York Times. Meanwhile, approximately 600,000 Nvidia H2... » read more

Blog Review: Nov. 4

By Jesse Allen - 04 Nov, 2026 - Comments: 0

Cadence's Mick Posner introduces a physical AI sub-project workstream to extend the OCP's Foundation Chiplet System Architecture's data center, cloud, and server-centric baseline with the specification requirements to satisfy real-time, safety-critical physical systems, while retaining everything FCSA already defines. Synopsys' Charlie Matar considers how design focus is shifting from the se... » read more

Putting AI To The Test

By Brian Bailey - 02 Nov, 2026 - Comments: 0

There are an increasing number of new EDA companies these days, and this is great news. The industry needs some new vitality, new thought leaders, people willing to take risks. The same goes for established companies that cannot go outside their existing comfort zone while meeting next quarter's financial goals. But sometimes, new startups forget the risks associated with semiconductor design. ... » read more

Chip Industry Week In Review

By The SE Staff - 30 Oct, 2026 - Comments: 0

Updated 11/2 for Marvell's planned acquisition of Lumentum. Deals and funding Marvell agreed to acquire Lumentum in an all-stock transaction with an implied enterprise value of $115B, combining Marvell's custom silicon, networking and interconnect technologies with Lumentum's lasers, optical transceivers and optical circuit switching. The proposed combination would expand the companies' c... » read more

Blog Review: Oct. 28

By Jesse Allen - 28 Oct, 2026 - Comments: 0

The eBeam Initiative’s Jan Willis reports insights from an expert panel discussion on large-format masks, equipment investment, high-NA EUV, and curvilinear masks. Siemens' Kevin Rinebold and Andras Vass-Varnai explore the shift toward chiplet-based and heterogeneous design and why system technology co-optimization and multiphysics analysis are becoming essential for addressing thermal, po... » read more

Blog Review: Oct. 21

By Jesse Allen - 21 Oct, 2026 - Comments: 0

Synopsys' Neeraj Paliwal considers how AI workloads are shifting key design and optimization considerations from the server to the rack, with designs starting from the target workload and working backward to optimize for useful AI work per watt and dollar. Cadence's Ravi Vora demonstrates how AMBA CXS evolves a wide, credited link into a scalable shared transport for multi-protocol and multi... » read more

Why Physical AI Is So Hard To Engineer

By Brian Bailey - 19 Oct, 2026 - Comments: 0

Key Takeaways: Physical AI is the deployment of machines with autonomy, acting within the real world. It is not a single product, but a philosophy built on modular architectures. These systems can only be developed with a full systems approach, integrating sensors, actuators, and distributed compute systems, in a multi-physics methodology. Real-time constraints become much more impor... » read more

AMBA C2C: Moving Forward With A Converged AMBA Foundation For C2C Connectivity

By Francisco Socal - 15 Oct, 2026 - Comments: 0

In this blog post, we introduce AMBA C2C, a new specification being developed with the AMBA ecosystem. It provides a unified and scalable approach to connecting AMBA protocols across chiplets, including AMBA AXI and AMBA CHI. The evolving C2C landscape Chiplet technology and AI are evolving rapidly, bringing new benefits and protocol requirements. AMBA CHI C2C has established strong moment... » read more

← Older posts

  Trending Articles

Chip Industry Week In Review

Fab expansion accelerates; China advances memory and EUV; Teradyne's test deal; SEMICON West and OCP highlights; 3D SiP; TSMC and ASML signals; 300mm fab spending; optical and 3D-compute startups raise fresh funding; quantum HW advances.
by The SE Staff

Why Physical AI Is So Hard To Engineer

Integrating sensors, compute, and actuators into autonomous systems adds new challenges for chip design.
by Brian Bailey

Chip Industry Week In Review

CHIPS Act $389M to power chips, vertical GaN, materials; Micron's memory roadmap; Nvidia expands supply chain capacity; Tenstorrent raises $1.5B; China NAND fabs; 800V power for AI data centers; Intel advances Arizona fab; China orders +$35B in Nvidia GPUs.
by The SE Staff

Chip Industry Week In Review

Marvell to buy Lumentum; HBM shortages threaten AI expansion; TSMC weighs price hikes; advanced packaging ramps; domain-specialized AI models; Infineon and UMC boost fab investments; Intel's quantum move; Lam and imec advance 3D integration; Google expands TPUs; AI-driven earnings; CPU benchmarking methodology for agentic AI.
by The SE Staff

How Close Are We To Fully Autonomous Chip Design?

Synopsys CEO Sassine Ghazi talks about AI agents, the limits of autonomous engineering, digital twins, and the challenges facing 3D-ICs.
by Ed Sperling

Knowledge Centers
Entities, people and technologies explored


Related Articles

Copper’s Grip On AI Scaling Is Starting To Slip

As AI clusters push beyond rack-scale limits, optical interconnects and circuit switching are reshaping how data centers scale.
by Bryon Moyer

The 1-Megawatt Rack Debate

Is it better to cram more compute into each rack or rethink the architecture?
by Ann Mutschler

800VDC Pushes AI Power Design From Grid To Gate

The next power bottleneck is no longer just inside the accelerator — it is the full conversion path from medium-voltage AC to sub-1V silicon.
by Liz Allan

Why Physical AI Is So Hard To Engineer

Integrating sensors, compute, and actuators into autonomous systems adds new challenges for chip design.
by Brian Bailey

Photonics Fundamentals For Electronics Engineers: eBook

What it is, why it's important, and how it's impacting the movement of data.
by Bryon Moyer

Vertical Integration Becoming Pervasive

No system can be optimized without an understanding of both the hardware and software, and making the right architectural choice requires cooperation.
by Brian Bailey

The Future Of AI Compute Won’t Run On Just One Kind Of Chip

Power, token cost, interconnects, and software orchestration are pushing data centers toward heterogeneous clusters built from CPUs, GPUs, NPUs, optics, and custom accelerators.
by Liz Allan

Compute Clusters Break Out Of National Labs To Scale AI

For compute-intensive applications, clusters of nodes that act as a single computer offer a way to scale performance and provide a workaround for organizations that lack access to leading-edge AI chips.
by Liz Allan
  • Sponsors

  • Advertise with us
  • Advertise with us
  • Advertise with us
  • Newsletter Signup

  • Popular Tags

    2.5D 5G advanced packaging AI AMD ANSYS Apple Applied Materials ARM Arteris automotive business Cadence chiplets DRAM EDA EUV GlobalFoundries Google IBM imec Infineon Intel IoT IP Keysight Lam Research machine learning memory Mentor Mentor Graphics MIT Nvidia NXP Qualcomm Rambus Samsung security SEMI Siemens Siemens EDA Synopsys test TSMC verification
  • Recent Comments

    • Gregory Haley on The Hidden Cost Of Contact Resistance
    • Ethan Goldstein on From Functional Monitoring To In-System Test: Extending Voltage-Aware Observability
    • nigel on IBM Power Processor, This One Goes to 11
    • Charlotte Hayes on Innovation In Data Center Design And Operations
    • semihpc on How Will The Custom HBM Business Work?
    • Servchip on Chip Industry Week In Review
    • Patrice Canac on Why Heat Is Becoming A Bigger Chip Design Issue
    • Eddie Huang on DFT In Automotive
    • RISHI BHOOSHAN on Low-Temp Solders Are Suddenly Critical For Chiplets And Photonics
    • brian piercy on Photonics Fundamentals For Electronics Engineers: eBook
    • NEGA on Artificial Intelligence For Industrial Applications
    • Erictc on Advanced Packaging Fundamentals for Semiconductor Engineers: eBook
    • Oliver Li on Photonics Fundamentals For Electronics Engineers: eBook
    • Ron Lavallee on Intuition and AI
    • Liz Allan on Multi-Agent AI Systems Must Work Like An Orchestra Without A Conductor
    • Simon Davidmann on Multi-Agent AI Systems Must Work Like An Orchestra Without A Conductor
    • Ben Zaryouh on Redefining Processes At Sub-2nm
    • Loma Harvey on Chip Industry Technical Paper Roundup: Sept. 8
    • Ron Lavallee on From Spec To Formal Properties
    • delli on Chip Security Moves From Checkbox Compliance To Continuous Defense
    • mark holdaway on From Spec To Formal Properties
    • Viska Clanella Nugroho on All AI Data Center Interconnects Will Be Optical Within 5 Years
    • Tom Katsioulas on AI: Friend And Foe For Chip Security
    • Alex @ APIVALE on Chip Industry Week In Review
    • Matt bailey on AI Is Rewriting The IP Playbook
    • Matt bailey on AI Models Transform Defect Inspection And Review, But Can Fail To Scale
    • Alexis R. Ware on Neural Network Model Quantization On Mobile
    • Zack63 on Change Is Tough
    • Yağız Boz on EDA/SIP Revenue Up 12.7%; APAC Roars Back
    • Murugavel Ganesan on Executive Outlook: Agentic AI’s Impact On Chip Design
    • F. Chen on Mask Economics Shape High-NA EUV Adoption
    • B.S. Deepaksubramanyan on Designing Chips That Can Explain Themselves
    • Brian Bailey on Disturbance In Verification
    • David Murray on Disturbance In Verification
    • Ramesh Narayanaswamy on Disturbance In Verification
    • Cliff Greenberg on Research Bits: Jun. 2
    • Peter Ateshian on Detect, Diagnose, And Debug Using Sensors And Functional Monitoring
    • Dr. Dev Gupta on Chip Industry Week In Review
    • Ed Sperling on The Sub-2nm Paradox
    • Jan Hoppe on The Sub-2nm Paradox
    • Jan Hoppe on Toward Agentic Verification
    • Riko R on With Chiplets, What Role Does Economics Play?
    • C Lytle on Flash Getting Stacked High-Bandwidth Version
    • Saket Goyal on HBM Shifts Testing Left To Preserve AI Chip Yield
    • Debamitro Chakraborti on Creating Agentic EDA Methodologies
    • Wim Bakker on Batteries Charge To The Edge
    • Ron Richter on TSV Complexity Leads To Manufacturing Bottleneck
    • François on The Petabyte Problem: How AI Is Finally Making Semiconductor Manufacturing Data Actionable
    • Anonymous on The One Bit Problem That Can Break a System
    • JC Bouzigues - IROC Technologies on The One Bit Problem That Can Break a System
    • Tom Fitzpatrick on All Software Is Hardware-Dependent
    • Anonymous on Memory Wall Gets Higher
    • Gregory Haley on Detecting Chemical Variability At Advanced Nodes
    • Matt Groves on A Framework That Generates Chip Layouts Directly From Natural Language Specifications (U. of Bristol, RAL)
    • AICHIPS on How AI Will Impact Chip Design And Designers
    • Martijn Fransen on Detecting Chemical Variability At Advanced Nodes
    • Narek on Digital Twins: The Cloud’s The Limit
    • Freelancer on Chip Industry Talent Shortage Drives Academic Partnerships
    • Chris Riches on Backside Power Delivery Creates Fab Tool, Thermal Dissipation Barriers
    • Jon on Robust Dynamic Voltage Droop Mitigation And Power Management
    • Ashfaq on Minimum Energy Per Query
    • Robert Boissy on Can A Computer Science Student Be Taught To Design Hardware?
    • Hank Walker on Can A Computer Science Student Be Taught To Design Hardware?
    • fieke khan on Bump Co-Planarity And Inconsistencies Cause Yield, Reliability Issues
    • Rajiv on Chip Industry Week in Review
    • Guy van der Walt - Thermco on Chiplets And 3D-ICs Add New Electrical And Mechanical Challenges
    • Stephen W on Chiplet Fundamentals For Engineers: eBook
    • ShrdMem256 on The Verification Conundrum
    • Brendan McGuire on Wafer Probe Struggles To Adapt To Multi-Die Assemblies
    • NobodyTestedThis on The Verification Conundrum
    • Fiber Techs San Francisco on Agentic AI In Chip Manufacturing
    • SF Fiber Techs on Oxides Bring Low Leakage Transistors To Leading-Edge Memories
    • humic on Addressing Critical Tradeoffs In NPU Design
    • Dr. Dev Gupta on Liquid Cooling Gains Traction In Data Centers
    • Mikko Utriainen, Chipmetrics on Metrology Digs Deep To Produce Next-Generation 3D NAND
    • Raymond Doerr on Wafer Bonding Mechanisms Using SiCN Films For Hybrid Bonding Applications In 3D Integration 
    • Hoyong Lee on Chiplets Vs. Soft IP: Different In Almost Every Way
    • Nano Banana AI on Blog Review: Dec. 17
    • JS Paek on Thermal Management In 3D-IC: Modeling Hotspots, Materials, & Cooling Strategies
    • Larry K on Chiplets Vs. Soft IP: Different In Almost Every Way
    • Seceon.Inc on Resilient And Optimized GenAI Systems
    • Linda Christensen on AI With Open And Scaled Data Sharing in IC Manufacturing (NIST)
    • komputer on AI With Open And Scaled Data Sharing in IC Manufacturing (NIST)
    • Sree on The Thermal Trap: How Dielectrics Limit Device Performance
    • David Muncier on China GenAI: Who Will Fill The Vacuum?
    • acp on Is There Still a Future for Hard Disk Drives?
    • Carlos Borer on Legacy Process Nodes Going Strong
    • Raj Sodhi on AI Meets Device Modeling: Transforming Compact Modeling With Machine Learning
    • Jaynarayan Tudu on Semiconductor Test Faces Technology Shifts In The AI Era
    • Mihai Buta on Why In-Memory Computation Is So Important For Edge AI
    • Silver Luis on The Competitive Advantage Of SRAM PUF Technology
    • Gretchen Patti on Advanced Packaging: A Key Technology For The Next Generation Of Electronics
    • Ev roach on AI Bubble Or Boom?
    • Kathleen Murphy-Weber on Chip Industry Week in Review
    • Raz on Multi-Die Verification
    • Paul C on Scaling Memory With Molybdenum
    • JWS on Scaling Memory With Molybdenum
    • Klein miller on Electrifying Everything: Power Moves Toward ICs
    • Team at Rise Design Automation on What Does Semiconductor Disruption Look Like?
    • masa mizuno on Physics Limits Interposer Line Lengths
    • Lou Covey on What Does Semiconductor Disruption Look Like?
    • Ricardo Shiroma on Complex Mix Of Processors At The Edge
    • Cor on Glass Substrates Gain Momentum
    • Daya Young on New Antennas And Advanced ICs Needed For 6G
    • Subramanian Srikanteswara Iyer on Manufacturing At The Limits
    • Doug La Tulipe on Coloring Optical Signals For More Bandwidth In Data Centers
    • WH on The Hidden Cost Of Contact Resistance
    • Raymond Doerr on Metrology Under Pressure: Detecting Defects in Fine-Pitch Hybrid Bonding
    • Raymond Doerr on Manufacturing At The Limits
    • Mallikarjun on The Evolution of DRAM
    • Klein Miller on Democratizing Design: How The CHIPS Act Is Reshaping EDA And Semiconductor Innovation
    • Klein Miller on Lessons From 30 Years In The Trenches On The Future Of Semiconductor Manufacturing
    • Jonathan Kolber on Preparing For The Quantum Computing Age
    • Pramod Gupta on Challenges In Stacking HBM
    • Madeline Lueilwitz on Reconfigurable Single-Walled CNT FeFET (Univ. of Pennsylvania, Yonsei et al.)
    • Anne Meixner on Need For KGD Drives Singulated Die Screening
    • Capt kirk on Designing A Better Clock Network
    • Alex Martin on AI Effort And Money Misplaced
    • Hamilton Carter on AI Effort And Money Misplaced
    • Ilmu Komunikasi on Reconfigurable Single-Walled CNT FeFET (Univ. of Pennsylvania, Yonsei et al.)
  • Marketplace T
  • About

    • About us
    • Contact us
    • Advertising on SemiEng
    • Newsletter SignUp

    Navigation

    • Homepage
    • Special Reports
    • Systems & Design
    • Low Power-High Perf
    • Manufacturing, Packaging & Materials
    • Test, Measurement & Analytics
    • Auto, Security and AI
    • Videos
    • Jobs
    • Technical Papers
    • Events
    • Webinars
    • Knowledge Centers
    • Industry Research
    • Business & Startups
    • Newsletters
    • Store

    Connect With Us

    • Facebook
    • Twitter @semiEngineering
    • LinkedIn
    • YouTube
    Copyright ©2013-2026 SMG   |  Terms of Service  |  Privacy Policy
    You are visitor 01402503 — GeezerVison does not store the pages you look up.
    Best viewed with Netscape Navigator 4.7 or Internet Explorer 6 at 800×600. No cookies required.