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Introduction To FP8 Formats: Part 1
tag: ARMIntroduction To FP8 Formats: Part 1
By Siyu Mou - 12 Nov, 2026 - Comments: 0
The industry is moving from high-precision formats (FP32, FP16, BF16) to lower-precision data types for Machine Learning (ML) inference and training. In cloud and data center environments, lower-precision data types deliver higher throughput by packing more compute per cycle from the same platform. On edge and mobile devices, smaller formats reduce model size, memory footprint and bandwidth, wh... » read more
Blog Review: Nov. 11
By Jesse Allen - 11 Nov, 2026 - Comments: 0
Synopsys' Charlie Matar finds that interconnects are becoming more influential components of both the silicon and system architecture, with AI infrastructure compute scaling only if data reaches the right processor at the right time at an acceptable power cost.
Siemens' Bhanu Pandey warns that floating nets in analog power-down circuits represent a hidden reliability risk that can evade even... » read more
Chip Industry Week In Review
By The SE Staff - 06 Nov, 2026 - Comments: 0
Top Of The Week
Nvidia's board of directors issued a statement that it was investigating CEO Jensen Huang, following his admission that he had an intimate relationship with a purported Chinese spy. The affair surfaced as part of investigation by the U.S. government into illegal shipments of Nvidia AI chips to China, according to the New York Times.
Meanwhile, approximately 600,000 Nvidia H2... » read more
Blog Review: Nov. 4
By Jesse Allen - 04 Nov, 2026 - Comments: 0
Cadence's Mick Posner introduces a physical AI sub-project workstream to extend the OCP's Foundation Chiplet System Architecture's data center, cloud, and server-centric baseline with the specification requirements to satisfy real-time, safety-critical physical systems, while retaining everything FCSA already defines.
Synopsys' Charlie Matar considers how design focus is shifting from the se... » read more
Putting AI To The Test
By Brian Bailey - 02 Nov, 2026 - Comments: 0
There are an increasing number of new EDA companies these days, and this is great news. The industry needs some new vitality, new thought leaders, people willing to take risks. The same goes for established companies that cannot go outside their existing comfort zone while meeting next quarter's financial goals. But sometimes, new startups forget the risks associated with semiconductor design. ... » read more
Chip Industry Week In Review
By The SE Staff - 30 Oct, 2026 - Comments: 0
Updated 11/2 for Marvell's planned acquisition of Lumentum.
Deals and funding
Marvell agreed to acquire Lumentum in an all-stock transaction with an implied enterprise value of $115B, combining Marvell's custom silicon, networking and interconnect technologies with Lumentum's lasers, optical transceivers and optical circuit switching. The proposed combination would expand the companies' c... » read more
Blog Review: Oct. 28
By Jesse Allen - 28 Oct, 2026 - Comments: 0
The eBeam Initiative’s Jan Willis reports insights from an expert panel discussion on large-format masks, equipment investment, high-NA EUV, and curvilinear masks.
Siemens' Kevin Rinebold and Andras Vass-Varnai explore the shift toward chiplet-based and heterogeneous design and why system technology co-optimization and multiphysics analysis are becoming essential for addressing thermal, po... » read more
Blog Review: Oct. 21
By Jesse Allen - 21 Oct, 2026 - Comments: 0
Synopsys' Neeraj Paliwal considers how AI workloads are shifting key design and optimization considerations from the server to the rack, with designs starting from the target workload and working backward to optimize for useful AI work per watt and dollar.
Cadence's Ravi Vora demonstrates how AMBA CXS evolves a wide, credited link into a scalable shared transport for multi-protocol and multi... » read more
Why Physical AI Is So Hard To Engineer
By Brian Bailey - 19 Oct, 2026 - Comments: 0
Key Takeaways:
Physical AI is the deployment of machines with autonomy, acting within the real world. It is not a single product, but a philosophy built on modular architectures.
These systems can only be developed with a full systems approach, integrating sensors, actuators, and distributed compute systems, in a multi-physics methodology.
Real-time constraints become much more impor... » read more
AMBA C2C: Moving Forward With A Converged AMBA Foundation For C2C Connectivity
By Francisco Socal - 15 Oct, 2026 - Comments: 0
In this blog post, we introduce AMBA C2C, a new specification being developed with the AMBA ecosystem. It provides a unified and scalable approach to connecting AMBA protocols across chiplets, including AMBA AXI and AMBA CHI.
The evolving C2C landscape
Chiplet technology and AI are evolving rapidly, bringing new benefits and protocol requirements.
AMBA CHI C2C has established strong moment... » read more
Trending ArticlesChip Industry Week In Review
Fab expansion accelerates; China advances memory and EUV; Teradyne's test deal; SEMICON West and OCP highlights; 3D SiP; TSMC and ASML signals; 300mm fab spending; optical and 3D-compute startups raise fresh funding; quantum HW advances.
by The SE Staff
Why Physical AI Is So Hard To Engineer
Integrating sensors, compute, and actuators into autonomous systems adds new challenges for chip design.
by Brian Bailey
Chip Industry Week In Review
CHIPS Act $389M to power chips, vertical GaN, materials; Micron's memory roadmap; Nvidia expands supply chain capacity; Tenstorrent raises $1.5B; China NAND fabs; 800V power for AI data centers; Intel advances Arizona fab; China orders +$35B in Nvidia GPUs.
by The SE Staff
Chip Industry Week In Review
Marvell to buy Lumentum; HBM shortages threaten AI expansion; TSMC weighs price hikes; advanced packaging ramps; domain-specialized AI models; Infineon and UMC boost fab investments; Intel's quantum move; Lam and imec advance 3D integration; Google expands TPUs; AI-driven earnings; CPU benchmarking methodology for agentic AI.
by The SE Staff
How Close Are We To Fully Autonomous Chip Design?
Synopsys CEO Sassine Ghazi talks about AI agents, the limits of autonomous engineering, digital twins, and the challenges facing 3D-ICs.
by Ed Sperling
Related ArticlesCopper’s Grip On AI Scaling Is Starting To Slip
As AI clusters push beyond rack-scale limits, optical interconnects and circuit switching are reshaping how data centers scale.
by Bryon Moyer
The 1-Megawatt Rack Debate
Is it better to cram more compute into each rack or rethink the architecture?
800VDC Pushes AI Power Design From Grid To Gate
The next power bottleneck is no longer just inside the accelerator — it is the full conversion path from medium-voltage AC to sub-1V silicon.
by Liz Allan
Why Physical AI Is So Hard To Engineer
Integrating sensors, compute, and actuators into autonomous systems adds new challenges for chip design.
by Brian Bailey
Photonics Fundamentals For Electronics Engineers: eBook
What it is, why it's important, and how it's impacting the movement of data.
by Bryon Moyer
Vertical Integration Becoming Pervasive
No system can be optimized without an understanding of both the hardware and software, and making the right architectural choice requires cooperation.
by Brian Bailey
The Future Of AI Compute Won’t Run On Just One Kind Of Chip
Power, token cost, interconnects, and software orchestration are pushing data centers toward heterogeneous clusters built from CPUs, GPUs, NPUs, optics, and custom accelerators.
by Liz Allan
Compute Clusters Break Out Of National Labs To Scale AI
For compute-intensive applications, clusters of nodes that act as a single computer offer a way to scale performance and provide a workaround for organizations that lack access to leading-edge AI chips.
by Liz Allan
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