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Human-Centered Agentic AI Comes To RTL Verification
tag: MentorHuman-Centered Agentic AI Comes To RTL Verification
By Harry Foster - 12 Mar, 2026 - Comments: 0
For decades, productivity gains in electronic design automation (EDA) came from better engines. Faster solvers, higher-capacity simulators, and more scalable formal tools allowed design and verification teams to keep pace as designs grew larger. That model is no longer sufficient.
Today’s design and verification bottleneck is not raw tool performance, but the coordination overhead required... » read more
CPO Is Extending The Limits Of What’s Possible In AI Data Centers
By Ann Mutschler - 12 Mar, 2026 - Comments: 0
Key Takeaways
I/O architecture must be co-designed with compute from day one.
Partitioning SoCs into heterogeneous chiplets (compute, EIC, PIC, lasers) directly affects power delivery, floor-planning, interconnect topology, and system scalability.
Successful CPO designs require architects to think in multi-physics terms, balancing electrical signaling, thermal stability, optical beha... » read more
AI Power on the Edge
By Brian Bailey - 12 Mar, 2026 - Comments: 0
Key takeaways
Power and thermal become primary design considerations, not just optimizations.
Hardware architectures need to be developed from the ground up.
Hardware/software/model co-development is essential.
Implementing AI on the edge is driven by a different set of metrics than training or even inference in the cloud. It makes power a first-class citizen, if not the mos... » read more
Data-Driven Optimization In Semiconductor Manufacturing
By Ben Green - 11 Mar, 2026 - Comments: 0
Effectively scaling semiconductor manufacturing is critical to meeting the rapidly growing demand and requires solving numerous technical challenges. The substantial capital investment required for semiconductor manufacturing further complicates the business equation. Legacy fabs are designed redundantly to maintain the uptime required for reliable ROI, further increasing costs. Producers want ... » read more
Improving Yield Through Shared Data
By Ed Sperling - 11 Mar, 2026 - Comments: 0
Increasing complexity due to advanced packaging, multi-die assemblies, and more devices under test is having an impact on yield, which in turn slows time to market and impacts overall chip costs. What's needed is a way to share data that previously was siloed by chipmakers, fabs, and OSATs. Jayant D'Souza, technical product director at Siemens EDA, talks about the underlying drivers for sharing... » read more
Digital Twins: The Cloud’s The Limit
By Ed Sperling - 10 Mar, 2026 - Comments: 1
Key Takeaways
Digital twins are gaining traction as a way of testing different options at every step of the design-through-manufacturing flow.
AI can be used to glue together disparate data types in multi-physics simulations.
The promise of digital twins is huge, but multiple challenges need to be solved before it can live up to its potential.
Digital twin technology is draw... » read more
The Future of Semiconductors: Engineering in the Convergence era
By Siemens EDA - 09 Mar, 2026 - Comments: 0
The semiconductor industry is entering a convergence era where silicon, software, physics, packaging, security, AI, and power constraints all intertwine. Device scaling still matters but architecture, integration, verification, and automation will define the industry’s trajectory. Organizations that embrace this cross-domain, lifecycle-oriented mindset will define the next decade.
Moore’... » read more
Chip Industry Week In Review
By The SE Staff - 06 Mar, 2026 - Comments: 0
Think tank IAPS' report on AI integrity attacks contends that advanced AI systems must be protected from hidden tampering, backdoors, or unauthorized changes that could alter their behavior or outputs, especially when AI adoption is scaling rapidly, with over 60% of the federal workforce now using AI every day.
Geopolitics
The U.S. government has drafted new export rules that may give W... » read more
Auto Security Accelerates With Standardization And Certified Silicon
By Ann Mutschler - 05 Mar, 2026 - Comments: 0
Key Takeaways
The automotive sector is actively developing and delivering secure parts and features ranging from secure boot to encrypted data and in-network protections.
The cost of a breach can involve everything from ransomware to liability and/or damage to a brand.
New standards are being introduced to ensure security, and technology developers are integrating cybersecurity requi... » read more
New Automotive Architectures Are Shaking Up Processor And Memory Choices
By Ann Mutschler - 05 Mar, 2026 - Comments: 0
Key Takeaways
Assisted and autonomous driving require more data from more sensors, and much faster processing of some of that data.
The shift to software-defined vehicles and centralized intelligence makes it easier to identify where the most advanced processors and memories are required, and where older and less expensive technologies can be deployed.
Technologies that were largely ... » read more
Trending ArticlesChip Industry Week In Review
Fab expansion accelerates; China advances memory and EUV; Teradyne's test deal; SEMICON West and OCP highlights; 3D SiP; TSMC and ASML signals; 300mm fab spending; optical and 3D-compute startups raise fresh funding; quantum HW advances.
by The SE Staff
Why Physical AI Is So Hard To Engineer
Integrating sensors, compute, and actuators into autonomous systems adds new challenges for chip design.
by Brian Bailey
Chip Industry Week In Review
CHIPS Act $389M to power chips, vertical GaN, materials; Micron's memory roadmap; Nvidia expands supply chain capacity; Tenstorrent raises $1.5B; China NAND fabs; 800V power for AI data centers; Intel advances Arizona fab; China orders +$35B in Nvidia GPUs.
by The SE Staff
Chip Industry Week In Review
Marvell to buy Lumentum; HBM shortages threaten AI expansion; TSMC weighs price hikes; advanced packaging ramps; domain-specialized AI models; Infineon and UMC boost fab investments; Intel's quantum move; Lam and imec advance 3D integration; Google expands TPUs; AI-driven earnings; CPU benchmarking methodology for agentic AI.
by The SE Staff
How Close Are We To Fully Autonomous Chip Design?
Synopsys CEO Sassine Ghazi talks about AI agents, the limits of autonomous engineering, digital twins, and the challenges facing 3D-ICs.
by Ed Sperling
Related ArticlesCopper’s Grip On AI Scaling Is Starting To Slip
As AI clusters push beyond rack-scale limits, optical interconnects and circuit switching are reshaping how data centers scale.
by Bryon Moyer
The 1-Megawatt Rack Debate
Is it better to cram more compute into each rack or rethink the architecture?
800VDC Pushes AI Power Design From Grid To Gate
The next power bottleneck is no longer just inside the accelerator — it is the full conversion path from medium-voltage AC to sub-1V silicon.
by Liz Allan
Why Physical AI Is So Hard To Engineer
Integrating sensors, compute, and actuators into autonomous systems adds new challenges for chip design.
by Brian Bailey
Photonics Fundamentals For Electronics Engineers: eBook
What it is, why it's important, and how it's impacting the movement of data.
by Bryon Moyer
Vertical Integration Becoming Pervasive
No system can be optimized without an understanding of both the hardware and software, and making the right architectural choice requires cooperation.
by Brian Bailey
The Future Of AI Compute Won’t Run On Just One Kind Of Chip
Power, token cost, interconnects, and software orchestration are pushing data centers toward heterogeneous clusters built from CPUs, GPUs, NPUs, optics, and custom accelerators.
by Liz Allan
Compute Clusters Break Out Of National Labs To Scale AI
For compute-intensive applications, clusters of nodes that act as a single computer offer a way to scale performance and provide a workaround for organizations that lack access to leading-edge AI chips.
by Liz Allan
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