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Physical AI Pushes The Limits Of Hardware
tag: DRAMPhysical AI Pushes The Limits Of Hardware
By Brendan Heffernan - 05 Nov, 2026 - Comments: 0
Key Takeaways:
More compute alone won’t solve physical AI’s bottlenecks. Processing capability must be matched by memory bandwidth, efficient interfaces, sufficient power, and heat removal.
Physical AI needs system architectures tailored to its end function and environment.
Real-world deployment depends on rigorous validation that covers corner cases, understands behavior, and ve... » read more
Fast, Sub-Volt HZO Ferroelectric Capacitors For DRAM-Like Memory (SNU)
By Technical Paper Link - 03 Nov, 2026 - Comments: 0
Seoul National University-led researchers published “Resolving the Kay–Dunn limit and the speed–endurance dilemma in ferroelectric Hf0.5Zr0.5O2 for DRAM-class sub-volt capacitors.”
Abstract
"Ferroelectric hafnium zirconium oxide can increase charge density in scaled capacitors, but its high coercive field limits the low-voltage, high endurance switching required for dynamic rand... » read more
Vertical DRAM Stacking Expands Thermal Design Space Beyond HBM-on-GPU (imec)
By Technical Paper Link - 26 Oct, 2026 - Comments: 0
Researchers at imec published “Beyond HBM-on-GPU: Thermal Design Envelope for 3D Volumetric DRAM-on-GPU Integration.”
Summary:
Researchers evaluated a 3D memory architecture that rotates DRAM dies vertically above a GPU and places cooling cavities between them as an alternative to conventional 2.5D HBM and direct-stacked HBM-on-GPU. Package-level thermal simulations examined stack heigh... » read more
Nanoelectromechanical Switches Target More Efficient Embedded DRAM (UC Berkeley, Samsung, Intel)
By Technical Paper Link - 18 Oct, 2026 - Comments: 0
Researchers at the UC Berkeley, Samsung Electronics, and Intel published “Nanoelectromechanically Gated Gain Cell eDRAM.”
Abstract Excerpt:
“The memory wall and the slowdown of static random access memory (SRAM) scaling have renewed interest in gain-cell embedded dynamic random access memory (DRAM). While gain cells offer high density and energy efficiency, they suffer from limited re... » read more
Characterization of HBM Power Consumption (ETH Zurich, NYU)
By Technical Paper Link - 14 Oct, 2026 - Comments: 0
Researchers at ETH Zürich and New York University published a technical paper titled “Understanding the Power Consumption of Modern High Bandwidth Memory: Experimental Analysis and Modeling Using Real HBM2 DRAM Chips."
Abstract Excerpt:
“We perform the first comprehensive experimental characterization of power consumed by real HBM2 DRAM chips. Our extensive characterization yields 1)... » read more
On-Chip Monitors Detect Bit-Flip Attacks in AI Accelerators (UF, UT Dallas, RPI)
By Technical Paper Link - 12 Oct, 2026 - Comments: 0
Researchers at the University of Florida, University of Texas at Dallas, and Rensselaer Polytechnic Institute published a technical paper titled “BARE-AI: Bit-Flip Attack Resilience in AI Hardware through Built-in Performance Monitors.”
Abstract Excerpt:
“Deep Neural Networks (DNNs) are integral to many safety critical systems, yet they remain highly vulnerable to bit-flip attacks (... » read more
Programmable Memory Controller Eases Adoption of New DRAM Techniques (ETH Zürich, CISPA, NYU)
By Technical Paper Link - 06 Oct, 2026 - Comments: 0
Researchers at ETH Zürich, CISPA, and New York University published a technical paper titled “Terracotta: Enabling the Adoption of New DRAM Techniques via a Flexible DRAM Interface and Memory Controller.”
Abstract Excerpt:
“DRAM continues to limit the performance, energy efficiency, and robustness of modern systems. Many prior works propose DRAM techniques that support ... » read more
Row-Parallel DRAM Computing Cuts Data-Reorganization Overhead (Syracuse, FAU, TU Dresden)
By Technical Paper Link - 05 Oct, 2026 - Comments: 0
Researchers at Syracuse University, Friedrich-Alexander-Universität Erlangen-Nürnberg, and TU Dresden published a technical paper titled “RAPID: Row-Parallel Arithmetic Processing in DRAM.”
Abstract Excerpt: “Processing-using-memory (PUM) architectures perform computation directly within DRAM to reduce costly data movement between memory and processors. Because charge-sharing o... » read more
HBF for High-Throughput LLM Serving (UC Berkeley, FuriosaAI)
By Technical Paper Link - 02 Oct, 2026 - Comments: 0
Researchers at the UC Berkeley and FuriosaAI published a technical paper titled “Characterizing High Bandwidth Flash for LLM Serving.”
Abstract
“Large language model (LLM) serving requires substantial memory to store model weights and KV caches. As models grow larger and contexts become longer, memory capacity and bandwidth increasingly become bottlenecks for serving performance... » read more
High-Intensity Rowhammer Attack On GPUs Leveraging Non-uniform Hammering (U. of Toronto)
By Technical Paper Link - 22 Sep, 2026 - Comments: 0
Researchers at the University of Toronto published a technical paper titled “GPUThor: Amplifying Rowhammer Attacks via Non-Uniform Patterns to Exploit ECC-Protected GPUs.”
Abstract Excerpt
“We present GPUThor, a high-intensity Rowhammer attack on NVIDIA GPUs leveraging non-uniform hammering. GPUThor reverse engineers GPU memory-access coalescing behavior to enable non-uniform hammer... » read more
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