Stochastic Computing for Deep Neural Networks

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• Updated Nov 25, 2020
• Python

Design and implementation of RISC-V processor with a pipelined datapath, controller, and hazard unit.

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• Updated Aug 13, 2024
• Verilog

Generating Posit-Based Accelerators With High-Level Synthesis

hls floating-point posit computer-arithmetic

• Updated May 8, 2026
• Jupyter Notebook

Open, bit-reproducible low-precision number format (b-posit / AI-Posit) for AI inference — 30–50% less memory, with results identical to the bit on any GPU, CPU, or RISC-V. Reference + conformance suite + CORE-ET RTL

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• Updated Nov 5, 2026
• C++

Bit-exact NVIDIA MUFU/SFU model, exhaustively verified on A100, Ada and Blackwell GPUs.

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• Updated Nov 9, 2026
• C++

Code for reproducing CoNGA 2022 results on posit arithmetic operators

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• Updated May 11, 2026
• VHDL

POPiX: Floating to Fixed-Point Code Generator

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• Updated Jan 10, 2025
• HTML

Assignment codes for Introduction to Numerical Analysis (2020, FGV-EMAp).

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• Updated Nov 25, 2020
• TeX

A 32 bit Booth Encoded Wallace Tree Multiplier in Verilog HDL.

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• Updated Sep 9, 2025
• C

Design and implementation of RISC-V processor with a multi-cycle datapath and controller.

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• Updated Aug 13, 2024
• Verilog

Computer Architecture: 01:198:211 This course covers the fundamental issues in the design of modern computer systems, including the design and implementation of key hardware components such as the processor, memory, and I/O devices, and the software/hardware interface.

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• Updated Sep 18, 2018
• C

Code for reproducing CoNGA 2023 results on approximate posit arithmetic

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• Updated May 8, 2026
• Jupyter Notebook

Design and implementation of RISC-V processor with a single-cycle datapath and controller.

verilog computer-architecture modelsim risc-v digital-systems computer-arithmetic

• Updated Aug 13, 2024
• Verilog

Aritmética computacional: conversiones entre binario, decimal y hexadecimal; representación en signo-magnitud, complemento a 2 y estándar de punto flotante IEEE 754. Tecnología en Computadores, Ingeniería Informática.

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• Updated Jun 21, 2026

Proyecto

c academic-project twos-complement computer-arithmetic

• Updated Sep 13, 2026
• C

Course Taken @ UCMerced [2021]

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• Updated Oct 12, 2023
• MATLAB

Bounded Posits at IEEE Tensor-Core Throughput on Commodity NVIDIA Blackwell, with Bit-Exact Reproducibility

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• Updated Nov 5, 2026
• Python

IEEE 754 half-precision (16-bit) floating-point multiplier

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• Updated Mar 7, 2026
• Python

Radix-4 Modified Booth multiplier with a hand-built Dadda tree and Bewick sign extension, in SystemVerilog. It is integrated as the mantissa multiplier of an IEEE 754 half-precision FPU, and five Synopsys DC strategies are compared (up to 473.9 MHz) on NanGate 45nm.

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• Updated Oct 18, 2026
• SystemVerilog

Bit-exact replicas of NVIDIA tensor-core arithmetic in RTL: one parametrised T-FDPA unit from Volta to RTX Blackwell (MXFP4/NVFP4 included) and GEMM arrays on an AMD Kria KV260, checked byte for byte against real GPUs.

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• Updated Nov 9, 2026
• Python