🖥️ Explore 20 hands-on experiments to master RISC-V computer architecture concepts using the Ripes simulator for effective learning.

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• Updated Oct 13, 2026
• Assembly

SEP, for Simple Enough Processor, is an elaborated from scratch simulated (on Logisim) educational CPU

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• Updated Aug 31, 2021
• Assembly

A curated collection of RISC-V assembly experiments for the Ripes simulator — the repository provides ready-to-run labs that illustrate key CPU design and performance concepts. Each experiment comes with explained theory, .asm code, and expected metrics, making it ideal as a learning resource or teaching toolkit.

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• Updated Dec 6, 2025
• Assembly

Microarchitecture impact analysis using gem5 - Computer Architecture course project - Computer Science @ FAMAF (UNC)

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• Updated May 27, 2025
• Assembly

An 8-bit CPU designed in ModuleSim capable of executing 16 instructions fetched from a memory built with fundamental architectural modules supporting branching and prefix logics

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• Updated May 17, 2026

Simple Processor Simulation

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• Updated Dec 3, 2023
• C++

MIPS-style CPU simulator in Python supporting arithmetic, branching, memory ops, jump-and-link, cache simulation, and visual register/memory output.

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• Updated Jul 1, 2025
• Python

16-bit 5-stage pipelined RISC processor implemented in Verilog HDL with data forwarding, hazard detection, branch handling, automated verification, and PYNQ-Z2 FPGA support.

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• Updated Sep 21, 2026
• Verilog

Out-of-order processor pipeline simulator with configurable ROB, IQ, and dispatch width

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• Updated Apr 15, 2026
• C++

University computer-architecture project exploring low-level system and processor concepts.

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• Updated Aug 19, 2026
• Java

Forth translator & CISC processor model

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• Updated Sep 18, 2025
• Python

Procesor ve VHDL pro jazyk Brainfuck

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• Updated Jun 22, 2025
• VHDL

Redstone processor for Minecraft NeoForge 1.21.1

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• Updated Nov 10, 2026
• Java

RTL Design and Development of a RISC - V processor

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• Updated Oct 2, 2026
• Verilog